The scalability requirements of higher and higher density DRAM and logic CMOS devices has popularized the salicide process for source to drain connections using TiSi2 and ( more recently ) CoSi2.

The desirability of these salicide processes is well documented with low sheet resistivity properties offering improved access time in DRAM and faster microprocessor speeds.

Besides the obvious drawback in temperature stability of these salicides, the irregular reaction of titanium or cobalt with silicon during RTA processing can result in irregular or “rough” surface features in the salicide. Submicron contaminants (especially metallic species) introduced during in-line electrical test of Kerf structures with high wettability are not easily dislodged by conventional aqueous/ultrasonic cleaning steps. Solvent process cleaning steps can leave residues in the irregular “rough” salicide surface leading to interfacial films between the salicide and the subsequent via connection to overlying bit lines ( or metal one lines ).