The field of semiconductor materials and devices represents a unique challenge to microscopy and microanalysis because the standard of excellence is constantly changing. Driven by the imperative of Moore's law (illustrated in figure 1) - which predicts that the density of devices in a chip doubles every three years - the spatial resolution that must be achieved increases by a factor of two every five years. The problem of meeting this demand is further enhanced by the widespread sentiment that all e-beam tools used on semiconductors should operate at low beam energies (typically below lkeV). Finally, the increase in device packing density and the expected move to 30cm. diameter wafers as substrates for fabrication also means that the microscopist will be faced with the challenge of rapidly and reliably finding a given device or feature among the 108 or so similar features which are present.

The first need is to be able to monitor the basic steps of the fabrication process. Given the assumption that by the year 2001 devices will be built on 0.18μm design rules, it will then be necessary to perform critical dimension metrology with a precision of 2 to 3nm (see figure 2).