The nano-scale dimensions of next generation VLSI and ULSI devices will drive the development of a variety of new processing requirements. Currently device processing conditions from substrate cleaning to thin film deposition require temperatures in the range of 600°C to 1200°C. In order to realize a Si device circuit architecture which integrates Si/Ge structures or the needed super abrupt junctions of buried channel CMOS, low temperature processes must replace those in current production lines. For these processes to be successfully developed and implemented, proper characterization techniques must be used. In the case of epitaxy, cross-sectional TEM is the tool of choice. We will discuss the prominent role that TEM has played in the development of a new Si epitaxy technology. Recently, at the National Renewable Energy Laboratory (NREL), we have shown low temperature, 195°C to 400°C, Si epitaxy via hot-wire chemical vapor deposition- HWCVD. In the past HWCVD has been used to produce amorphous, micro-crystalline, and polycrystalline Si thin films.