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Analysis of Deep Level and Oxide Interface Defects Using 100V HF Schottky Diodes and MOS CV for Silicon and 4H SiC HV MOSFETs, Advanced Power Electronics, and RF ASIC

Published online by Cambridge University Press:  03 May 2019

J Pan*
Affiliation:
Advanced Technology Laboratory, Northrop Grumman Corporation, 1212 Winterson Road, Linthicum, Maryland, 21090, U.S.A.
S. Afroz
Affiliation:
Advanced Technology Laboratory, Northrop Grumman Corporation, 1212 Winterson Road, Linthicum, Maryland, 21090, U.S.A.
N. Crain
Affiliation:
Advanced Technology Laboratory, Northrop Grumman Corporation, 1212 Winterson Road, Linthicum, Maryland, 21090, U.S.A.
W. Henning
Affiliation:
Advanced Technology Laboratory, Northrop Grumman Corporation, 1212 Winterson Road, Linthicum, Maryland, 21090, U.S.A.
J. Oliver
Affiliation:
Advanced Technology Laboratory, Northrop Grumman Corporation, 1212 Winterson Road, Linthicum, Maryland, 21090, U.S.A.
T. Knight
Affiliation:
Advanced Technology Laboratory, Northrop Grumman Corporation, 1212 Winterson Road, Linthicum, Maryland, 21090, U.S.A.
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Abstract

In this paper we report high voltage MOS and Schottky Diode CV techniques for silicon and SiC power devices. 4H Silicon carbide is a wide bandgap semiconductor suitable for high voltage power electronics and RF applications due to high avalanche breakdown critical electric field, and thermal conductivity. The performance of various power devices, which may include MOSFET and Static Induction Transistor (SIT), can be affected by the deep level traps in the substrate and the oxide interfacial defects. We have characterized deep level trap (High Voltage Schottky Diode HF CV) and oxide interface trap densities (High Voltage HF MOS CV), measured the device channel doping profile for both 4H SiC and silicon, gate metal workfunction, and simulated the effects on DC/AC performance.

Type
Articles
Copyright
Copyright © Materials Research Society 2019 

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