Contact materials in Si-based devices

As Si devices have been scaled down in size, so has the contact area, resulting in increasing contact resistance. In fact, the overall contribution of contact resistance to the series resistance of metal oxide semiconductor field-effect transistors (MOSFETs) is expected to reach above 60% for the 32 nm node.Reference Kim, Park and Woo^4, Reference Kim, Narasimha and Rim⁵ There are two ways to reduce the contact resistance at the silicide-Si junctions (current values are in the upper 10^–8 Ω cm²). The first way, traditionally used, is a higher active doping concentration (N) in the junction. However, this approach is limited by the solid solubility of the dopant in Si and has basically reached the limit of its benefit. An additional method to reduce ρ_c is to lower the barrier height at the silicide-Si junction (a barrier height <0.3 eV is needed to get ρ_c below 1 × 10^–8 Ω cm²). The current preferred silicide (NiSi) forms relatively large barrier heights to n ⁺ and p ⁺ Si of 0.67 and 0.43 eV, respectively.Reference Kittl, Opsomer, Torregiani, Demeurisse, Mertens, Brunco, Van Dal and Lauwers⁶ Figure 1 summarizes the multiple approaches that can be leveraged to lower junction barrier heights to reduce ρ_c. One approach is to use a smaller bandgap material such as SiGe. In fact, SiGe junctions for p-channel devices have now been in production and provide a small reduction in the barrier height to Si (in addition to strain-enhanced mobility).Reference Ghani, Armstrong, Auth, Bost, Charvat, Glass, Hoffmann, Johnson, Kenyon, Klaus, McIntyre, Mistry, Murthy, Sandford, Silberstein, Sivakumar, Smith, Zawadzki, Thompson and Bohr⁷ Another approach is to use dual-silicide junctions, shown as the black and red regions above the source and drain, respectively, in Figure 1. One silicide is optimized for n ⁺-Si and the other for p ⁺-Si. This approach has been reported using PtSi for a p-type metal oxide semiconductor (PMOS) and ErSi_1.7 for an n-type metal oxide semiconductor (NMOS) (ϕ_p,ϕ_n = 0.22 eV, 0.3 eV, respectively).Reference Kedzierski, Xuan, Andew, Bokor, King and Hu⁸ Yet another method takes advantage of Fermi-level pinning using surface passivation to set the effective barrier height.Reference Ikeda, Yamashita, Sugiyama, Taoka and Takagi⁹ More details on this topic are found in the article by Loh and Coss in this issue.

Figure 1. Research directions in nanoscale complementary metal oxide semiconductor devices. These directions include junction silicide engineering, gate stack engineering, and incorporation of alternate channel materials. S/D is source/drain, ϕ_B is the barrier height, ϕ_m is the metal work function, and N _d is the doping density.

Increasingly, the introduction of new materials is driving improvements in Si transistor performance. One high profile example involving contacts is high-κ/metal gate materials.Reference Ito, Namba, Yamaguchi, Hirata, Ando, Koyama, Kuroki, Ikezawa, Suzuki, Saitoh and Horiuchi^10–Reference Gusev, Buchanan, Cartier, Kumar, DiMaria, Guha, Calegari, Zafar, Jamison, Nuemayer, Copel, Okorn-Schmidt, D’Emic, Kozlowski, Chan, Bojarczuk, Ragnarsson, Ronsheim, Rim, Fleming, Mocuta and Ajmera¹⁷ Because of its lower carrier concentration compared to metals, polycrystalline silicon (poly-Si) has always exhibited a carrier depletion effect, but its impact on transistor performance became significant only as the SiO₂ gate dielectric thickness dropped below 2.0 nm. To eliminate the poly-Si depletion effect, metal gate materials with work functions comparable to heavily doped n-type silicon (4.05 eV) and p-type silicon (5.15 eV) were needed. The realization of these work functions using metal gates deposited directly on Hf-based dielectrics was not trivial even as hundreds of contact materials and compositions were evaluatedReference Alshareef, Zhang, Majhi, Brown, Zeitzof, Huff and Lee^18–Reference Schaeffer, Samavedam, Gilmer, Dhandapani, Tobin, Mogab, Nguyen, White, Dakshina-Murthy and Rai²¹ (see Figure 2). The vast majority showed some level of Fermi-level pinning, making it difficult to get the appropriate threshold voltage, especially with gate oxides approaching 1 nm equivalent oxide thickness.Reference Hobbs, Fonseca, Knizhnik, Dhandapani, Samavedam, Taylor, Grant, Dip, Triyoso, Hegde, Gilmer, Garcia, Roan, Lovejoy, Rai, Hebert, Tseng, Anderson, White and Tobin^22–Reference Yeo, King and Hu²⁴ Ultimately, two solutions emerged to overcome this issue. One was interface engineering using angstrom-level dipole interfacial layers to shift the effective work function to the desired values (4.0 and 5.0 eV for the n- and p-type silicon layers, respectively). A particularly effective oxide for NMOS was La₂O₃,Reference Alshareef, Quevedo-Lopez, Wen, Harris, Kirsch, Majhi, Lee and Jammy^25–Reference Copel, Guha, Bojarczuk, Cartier, Narayanan and Paruchuri²⁷ and for PMOS, Al₂O₃ was effective.Reference Alshareef, Luan, Choi, Harris, Wen, Quevedo-Lopez, Majhi and Lee²⁸ The second approach was to use a lower thermal budget flow to exert better control on the interface chemistry, particularly oxygen.Reference Guha and Narayanan^29, Reference Shiraishi, Yamada, Torii, Akasaka, Nakajima, Konno, Chikyo, Kitajima and Arikado³⁰ Please see the article by Wen and Chambers in this issue for more details.

Figure 2. Effective work function of transistor gate contacts. The x-axis shows a large number of materials and compositions that have been tested as transistor metal gates. They include metals, conductive nitrides, silicides, oxides, and a combination of such materials.Reference Alshareef, Zhang, Majhi, Brown, Zeitzof, Huff and Lee^18, Reference Majhi, Wen, Alshareef, Harris, Luan, Choi, Park, Song, Lee and Jammy¹⁹

Electrical contacts to nanoscale devices

Si nanowires and carbon nanotubes (CNTs) have attracted significant attention for nanoelectronic device applications (see Figure 3).Reference Lu and Lieber^31–Reference Anantram and Léonard³³ While CNTs offer exceptional mobilities, Si nanowires stand to benefit from the vast existing Si industry experience. The realization of Si nanowire devices, such as planar devices, will require low resistance contacts, controlled Fermi-level pinning, controlled doping levels and profiles, and appropriate barrier heights to be achieved. Two things make Si nanowire devices different from their planar counterparts: their large surface area-to-volume ratio and their exceedingly small size. Since contact resistance increases with the inverse of contact area, contact resistance can be large for nanowire devices. Further, obtaining ohmic contacts by relying on heavy doping of Si or Ge nanowires may not be a viable approach because variation in dopant concentration of only a few atoms would significantly alter the contact resistance.Reference Hanrath and Korgel³⁴ Additionally, the realization of appropriate barrier heights may be equally challenging. This is because variation in Si nanowire size may lead to fluctuation in the bandgapReference Piscator and Engström^35–Reference Yao, Zhang and Li³⁷ and because interfacial phenomena such as Fermi level, E _F, pinning and interface trap density can show dramatic differences from planar devices.Reference Hasegawa, Sato and Kasai^38–Reference Svensson, Sourab, Tarakanov, Su. Lee, Park, Baek, Park and Campbell⁴¹ In fact, it has been reported that highly localized interfacial dipoles can form which, together with pinning of E _F, can result in nanoscale Schottky barriers 40% to 90% larger than the barrier at the corresponding bulk interface.Reference Landman, Barnett, Scherbakov and Avouris⁴² CNTs mostly form Schottky barrier heights, and surface treatments may be needed to reduce these barriers, while Si nanowires have been demonstrated with ohmic contacts.

Figure 3. Potential issues in contact development for nanowire devices.

Another type of nanoscale device being addressed here is the nanoelectromechanical switching device. Along with the common issues of contact resistance and barrier height, these devices will present a different set of challenges. These challenges include the requirement of low stress contacts and mechanical integrity of the contact interface with the active materials, particularly for the moving parts. Please refer to the article by Hussain and Song in this issue for more details.

Contact materials to Ge and III–V compounds

It is becoming clear that scaling of CMOS can only be realized by the continuous introduction of new materials (high-κ/metal gates,Reference Chau, Brask, Datta, Dewey, Doczy, Doyle, Kavalieros, Jin, Metz, Majumdar and Radosavljevic⁴³ SiGe-SiC,Reference Ghani, Armstrong, Auth, Bost, Charvat, Glass, Hoffmann, Johnson, Kenyon, Klaus, McIntyre, Mistry, Murthy, Sandford, Silberstein, Sivakumar, Smith, Zawadzki, Thompson and Bohr⁴⁴ GeReference Yu, Ishibashi, Park, Kobayashi and Saraswat⁴⁵/III–V channelsReference Hu, Saraswat and Philip Wong⁴⁶) and/or architectures (such as FinFETReference Kedzierski, Fried, Nowak, Kanarsky, Rankin, Hanafi, Natzle and Boyd⁴⁷ [fin-shaped field-effect transistor] and triple-gated transistors,Reference Kavalieros, Doyle, Datta, Dewey and Chau⁴⁸ and nanowiresReference Li, Yeo, Suk, Yeoh, Kim, Chung, Oh and Lee⁴⁹). High mobility materials are strong contenders to replace Si in future generation low-power devices. These materials provide an intrinsic mobility enhancement in excess of five times over Si and hence pose a much more stringent requirement on contact resistance (to keep the external resistance, R _ext, a small fraction of the total resistance). To realize the true potential of devices with Ge and/or III–V channels, it is estimated that the contact resistivities for these systems should be below 10^–8 Ω cm². One needs to comprehend the nanostructure of the metal-semiconductor contact and correlate this to the electrical properties of the contact. Interestingly, it has been demonstrated that most metals in contact with p-Ge have their work function pinned to the valence band of Ge, making it easier to form ohmic contacts to Ge for pFETs. However, for nFETs this Fermi-level pinning toward the valence band edge E _v results in a very high interfacial resistance. Some research groups have demonstrated promise in tuning this resistance by inserting a thin layer that modulates the pinning while being transparent and allowing high tunneling currents. Nevertheless, there is limited experimentally demonstrated low R _co for metal-Ge (n-type) contacts. For the III–V systems, there has been significant research on making low resistance contacts to an In-Ga-As semiconductor. The various approaches include the modulation of the interface to tune the Schottky barrier height and increasing the semiconductor dopant densities to 10²⁰/cm³ levels by in situ doped junctions. It has also been surmised that the higher dopant densities create an interfacial dipole that further reduces the effective Schottky barrier height of the metal/III–V contacts. Additionally, modulation of the contact resistivity using a metal-insulator-semiconductor structure is being researched with limited, but promising, results. The article by Hu et al. in this issue summarizes the current understanding of contacts to Ge and III–V semiconductors and ongoing research directions.

Contact materials to thin-film transistors

Thin-film transistors (TFTs) have become a key technology for the electronic flat panel industry in the past 15 years, just as silicon chips have been a key technology for the electronics revolution. Multiple factories today produce millions of displays per year, with each display incorporating several million TFTs. The concept of the TFT and its potential utility significantly pre-dated the device that gave rise to the term transistor.Reference Lilienfeld⁵⁰ However, for many years, it was overshadowed by the astounding developments associated with the original bipolar transistor and the MOSFET. In more than six decades, thin-film transistors have undergone extensive evolution, development, and optimization. During this period of time, their intended uses went from switching systems to low-cost computer logic to flat panel displays, and new materials, structures, and fabrication techniques were introduced. TFT-based CMOS devices have also been demonstrated (Figure 4).Reference Quevedo-Lopez, Gowrisanker, Alshareef, Gnade, Venugopal, Krishna, Kaftanoglu and Allee^51, Reference Gowrisanker, Ai, Jia, Quevedo-Lopez, Alshareef and Gnade⁵²

Figure 4. Complementary metal oxide semiconductor (CMOS) fabricated in thin-film transistor (TFT) technologies. Top left: Cross-section of the CMOS structure comprising both organic and inorganic thin-film transistors. Top right and bottom left and right: test structures.Reference Quevedo-Lopez, Gowrisanker, Alshareef, Gnade, Venugopal, Krishna, Kaftanoglu and Allee^51, Reference Gowrisanker, Ai, Jia, Quevedo-Lopez, Alshareef and Gnade⁵²

For conventional semiconductors, including single crystal and amorphous silicon, ohmic contacts are most often formed using heavily doped semiconductor regions at metal-semiconductor interfaces. However, most oxide and organic TFT devices do not use doping to help form ohmic contacts. Instead, electrodes directly contact semiconductor regions with negligible or low doping. As a result, many oxide and organic TFTs have non-ohmic contacts. In fact, many oxide and organic semiconductor TFTs operate with Schottky source contacts, where gate field-induced charge is used to provide carriers not present from doping to allow tunneling between the source electrode and the TFT channel.Reference Sun and Rogers⁵³ Despite the considerable progress made in recent years to improve the performance of organic and oxide TFTs, many issues are still poorly understood and poorly controlled. With decreasing device dimensions, the contact resistance as a part of the total device resistance will dominate compared with channel resistance, and therefore will play an important part in TFT operation, as well. This can be alleviated either by performing surface preparation to reduce the metal semiconductor barrier height or by increasing the effective carrier concentration of the surface, perhaps taking advantage of interface engineering.

Summary

The effect of contact resistance on the performance of devices is becoming more pronounced as devices are scaled to the nanoscale. This reality will require increased ingenuity on the part of materials scientists to control interfacial reactions and to engineer the interface. Judging from the rate at which new materials and processes have entered the microelectronic and nanoelectronic industries, the prognosis for finding solutions to mitigate these issues is quite good.