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Development of porous SiLK™ Semiconductor Dielectric Resin for the 65 nm and 45 nm Nodes

Published online by Cambridge University Press:  01 February 2011

R. J. Strittmatter ,
J. L. Hahnfeld ,
H. C. Silvis ,
T. M. Stokich ,
J. D. Perry ,
K. B. Ouellette ,
Q. J. Niu ,
J. P. Godschalx ,
T. H. Kalantar  and
E. Mubarekyan
...Show all authors
R. J. Strittmatter
Affiliation:
Advanced Electronic Materials The Dow Chemical Company Midland, MI 48674USA
J. L. Hahnfeld
Affiliation:
Advanced Electronic Materials The Dow Chemical Company Midland, MI 48674USA
H. C. Silvis
Affiliation:
Advanced Electronic Materials The Dow Chemical Company Midland, MI 48674USA
T. M. Stokich
Affiliation:
Advanced Electronic Materials The Dow Chemical Company Midland, MI 48674USA
J. D. Perry
Affiliation:
Advanced Electronic Materials The Dow Chemical Company Midland, MI 48674USA
K. B. Ouellette
Affiliation:
Advanced Electronic Materials The Dow Chemical Company Midland, MI 48674USA
Q. J. Niu
Affiliation:
Advanced Electronic Materials The Dow Chemical Company Midland, MI 48674USA
J. P. Godschalx
Affiliation:
Advanced Electronic Materials The Dow Chemical Company Midland, MI 48674USA
T. H. Kalantar
Affiliation:
Advanced Electronic Materials The Dow Chemical Company Midland, MI 48674USA
E. Mubarekyan
Affiliation:
Advanced Electronic Materials The Dow Chemical Company Midland, MI 48674USA
R. E. Hefner Jr
Affiliation:
Advanced Electronic Materials The Dow Chemical Company Midland, MI 48674USA
J. W. Lyons
Affiliation:
Advanced Electronic Materials The Dow Chemical Company Midland, MI 48674USA
J. M. Dominowski
Affiliation:
Advanced Electronic Materials The Dow Chemical Company Midland, MI 48674USA
G. R. Buske
Affiliation:
Advanced Electronic Materials The Dow Chemical Company Midland, MI 48674USA
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Abstract

Porous SiLK resin is an ultra-low-k interlayer dielectric (ILD) material designed to meet the needs of the 65 nm technology node and beyond. In early 2002, the porous SiLK resin formulation was defined and scaled up, facilitating the tight monitoring and control of key properties, including pore size distribution, over several lots of material. The film processing kinetics are now well understood and a wide process window exists which ensures optimum pore morphology and pore size distribution. Thermal cycling of films demonstrates no effect on pore morphology or dielectric constant. The material has been designed to minimize the impact of CTE mismatch at high temperature, which challenged the integration of some previous generations of SiLK and porous SiLK dielectric resins. The discrete, closed-cell pore geometry is well characterized and enables the extendibility of process module development from SiLK resin technology to porous SiLK resin. Concurrent with the scale up efforts, advancements in minimizing both cure time and temperature simultaneously, as well as significant improvements in pore size and pore size distribution, have been achieved. The cure and porogen burn out time has been reduced by 50% or greater, and the temperature has been reduced to 370°C. The pore size has been reduced by ∼35%, and the pore size distribution has been narrowed by ∼40%. These advancements have resulted in the introduction of porous SiLK T resin, with a dielectric constant of k = 2.4 and a recommended cure temperature of 370°C, and the introduction of porous SiLK U resin, with a mean pore diameter of ∼5 nm and a dielectric constant of k = 2.2.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 766: Symposium E – Materials, Technology and Reliability for Advanced Interconnects and Low-k Dielectrics - 2003 , 2003 , E7.5
Copyright
Copyright © Materials Research Society 2003

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