Hostname: page-component-586b7cd67f-g8jcs Total loading time: 0 Render date: 2024-11-25T19:28:27.157Z Has data issue: false hasContentIssue false
  • English
  • Français

Effect of N+ Ion Implantation and Gox Process on in and B Channel Profile

Published online by Cambridge University Press:  17 March 2011

G. Curello ,
R. Rengarajan ,
J. Faul ,
H. Wurzer ,
J. Amon ,
T. Gaertner ,
D. Henke ,
M. Schmeide  and
A. Kieslich
G. Curello
Affiliation:
Technology Development Dept., i n f i n e o n technologies AG, Memory Products Division
R. Rengarajan
Affiliation:
Technology Development Dept., i n f i n e o n technologies AG, Memory Products Division
J. Faul
Affiliation:
Technology Development Dept., i n f i n e o n technologies AG, Memory Products Division
H. Wurzer
Affiliation:
Technology Development Dept., i n f i n e o n technologies AG, Memory Products Division
J. Amon
Affiliation:
Technology Development Dept., i n f i n e o n technologies AG, Memory Products Division
T. Gaertner
Affiliation:
Unit Processes Dept. - Koenigsbruecker Strasse 180, D-01099 Dresden, Germany
D. Henke
Affiliation:
Unit Processes Dept. - Koenigsbruecker Strasse 180, D-01099 Dresden, Germany
M. Schmeide
Affiliation:
Unit Processes Dept. - Koenigsbruecker Strasse 180, D-01099 Dresden, Germany
A. Kieslich
Affiliation:
Technology Development Dept., i n f i n e o n technologies AG, Memory Products Division
Get access

Abstract

In this work, we report on the effect of different dual gate oxide (DGox) processes on the electrical properties of CMOS devices in deep submicron embedded DRAM (eDRAM) technology. Also discussed, is the effect of N+ Ion Implantation on the diffusion / segregation behaviour of B and In channel dopants. In particular, it will be shown that the N+ dose required to obtain a certain combination of dual gate oxide thickness varies with the gate oxide process. Effects of N+ dose on the In and B channel profiles are studied using SIMS. The impact of “thickness-equivalent” DGox processes on short channel effect (SCE) and carrier mobility is analyzed and tradeoffs for optimization of device performances are discussed.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 610: Symposium B – Si Front End Processing - Physics & Technology..II , 2000 , B3.4
Copyright
Copyright © Materials Research Society 2000

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

[1] Gwoziecki, R., Skotnicki, T., Bouillon, P. and Gentil, P. “Optimization of Vth roll-off in MOSFET's with advanced channel architecture-retrograde doping and pockets,” IEEE Transactions on Electron Devices vol.46, no.7, p.1551-61 1999.10.1109/16.772510Google Scholar
[2] Skotnicki, T. and Bouillon, P. “Electrical Performances of retrograde versus conventional profile MOSFETs” Symp.VLSI Tech. Digest 1996, pag. 152–53.Google Scholar
[3] Togo, M., Noda, K. Tanigawa, T., “Multiple-thickness gate oxide and dual-gate technologies for high-performance logic-embedded DRAMs” IEDM Tech. Digest 1998, p.347–50.Google Scholar
[4] Wurzer, H., Feldner, K., Graf, W., Curello, G., Faul, J., Weber, D., Kieslich, A. “A 0.17um embedded DRAM technology with 0.23um2 cell size and advanced CMOS logic” Symp VLSI Tech. Dig. 2000.Google Scholar
[5] Faul, J., Vogelsang, T. and Hansch, W.. DRAM Development Alliance - IBM / Siemens / Toshiba internal rep. 1997.Google Scholar
[6] Yamanaka, T., Fang, S.J., Lin, H.C., Snyder, J.P., Helms, C.R. “Correlation between inversion layer mobility and surface roughness measured by AFM” IEEE Electr. Dev. Lett. 17, p.178, 1996.10.1109/55.485166Google Scholar