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Effects of Thin Film Stress in Sub Micron Multilevel Devices

Published online by Cambridge University Press:  22 February 2011

Sharad Prasad
Affiliation:
LSI LOGIC CORPORATION, 48660 Kato Road, Fremont CA 94539
Y.C. Lu
Affiliation:
3115 Alfred St., Santa Clara CA
D.K Li
Affiliation:
LSI LOGIC CORPORATION, 48660 Kato Road, Fremont CA 94539
G.S. Reddy
Affiliation:
LSI LOGIC CORPORATION, 48660 Kato Road, Fremont CA 94539
F. Chen
Affiliation:
3115 Alfred St., Santa Clara CA
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Abstract

Submicron high density devices require multilevel interconnections. In multilevel interconnections, issues relating to planarity, stress voiding of metals and stress cracking of the dielectric(s) play an dominant role.As the levels of interconnect go up so does the stress level. A high stress level in the intermediate dielectric can cause cracks which ultimately lead to device failure. In this paper we present a novel method to detect stress cracking using focussed ion beam. This method is correlated with wet chemical etch process and RIE.The phenomenum of cracking of dielectric(s) is studied and different technology aspects are considered. Using the focussed ion beam a robust dielectric is developed.

Type
Research Article
Copyright
Copyright © Materials Research Society 1994

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References

REFERENCES

[1] Prasad, S., Bruner, M., Chen, F., Gandhi, M., Lu, Y.C., Kao, C.Y., Yang, S., Hata, W. “A triple level metal process for high performance and high density 0.6 μm/5V application specific integrated circuits” in Multilevel Interconnections: Issues that Impact Competetiveness, Hoang, H.H., Schulz, Ron, Bernstien, J., Vasquez, B., Editors, Proc. SPIE 2090, pp 111 Google Scholar
[2] Yao, G. D., Lu, Y.C., Prasad, S., Hata, W., Chen, F.S., Zhang, H. “Electrical and Physical Charactrization of TiN Diffusion Barrier for Submicron contact structure” Mat. Res. Soc. Proc. 1993 Google Scholar