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Electromigration Failure Distributions for Multi-Layer Interconnects as a Function of Line Width: Experiments and Simulation

Published online by Cambridge University Press:  15 February 2011

D. D. Brown ,
J. E. Sanchez Jr ,
V. Pham ,
P. R. Besser ,
M. A. Korhonen  and
C.-Y. Li
D. D. Brown
Affiliation:
Advanced Micro Devices, Sunnyvale, CA 94088
J. E. Sanchez Jr
Affiliation:
Advanced Micro Devices, Sunnyvale, CA 94088 Now in the Materials Science Department, University of Michigan, Ann Arbor, MI 48109
V. Pham
Affiliation:
Advanced Micro Devices, Sunnyvale, CA 94088
P. R. Besser
Affiliation:
Advanced Micro Devices, Sunnyvale, CA 94088
M. A. Korhonen
Affiliation:
Materials Science Department, Cornell University, Ithaca, NY 14850
C.-Y. Li
Affiliation:
Materials Science Department, Cornell University, Ithaca, NY 14850
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Abstract

In narrow metal lines used for chip level interconnects, the line width can strongly affect the electromigration reliability, typically due to variations in the microstructure and in the mechanical stress state. These variations have a stronger effect as the line width decreases to the order of the metal grain size or less. Electromigration failure distributions were obtained both experimentally and by simulation for realistic interconnect structures with six different line widths, ranging from lμm to 8μm. In order to simulate the electromigration failure distributions, microstructure statistics were obtained (using TEM) and the critical void volume for failure was measured (using SEM) for each line width. The simulated failure times match the experimental failure times for narrow line widths (1-4μm).

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 427: Symposium K – Advanced Metallization for Future ULSI , 1996 , 107
Copyright
Copyright © Materials Research Society 1996

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