Embedding passives into printed wiring boards have numerous advantages that show up in different segments of the market. For example, the ability to locate decoupling capacitors within a couple hundred microns of semiconductor I/Os greatly improves response time and signal integrity leading to product performance improvements. One crucial need, however, is high capacitance density. High capacitance density can only be readily achieved by ceramic technology. Therefore, the focus of this work has been the development of ceramic thick-film capacitor technology that can be used to bury high capacitance density components within an organic substrate. This allows high value decoupling capacitors to be buried for chip packaging or related applications in spaces available within any layer of the substrate.

The dielectric paste is based on doped barium titanate composition and works together with a cofired copper electrode paste. The capacitor system is designed to be screen printed on copper foil in the locations desired in the circuit and fired in nitrogen at 900°C to form the ceramic components. Following this, the foil is laminated, component face down, to the organic laminate using standard prepreg and the inner layer etched to reveal the components in an organic matrix. The system has a dielectric constant of approximately 3000 and achieves a capacitance density of ∼1.5 nF/mm2. In the following sections, issues that we encountered when making embedded capacitors with this first generation system are presented.