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High-Current and Low Acceleration Voltage Arsenic Ion Implanted Polysilicon-Gate and Source-Drain Electrode Si MOS Transistor

Published online by Cambridge University Press:  25 February 2011

Yasuyuki Saito ,
Yoshiro Sugimura  and
Michiyuki Sugihara
Yasuyuki Saito
Affiliation:
Nichiden-Toshiba Info. Syst. Inc. (NTIS) res.lab. in Toshiba Horikawa-cho Works, 72, Horikawa-cho. Saiwai-ku, Kawasaki 210, Japan
Yoshiro Sugimura
Affiliation:
Nichiden-Toshiba Info. Syst. Inc. (NTIS) res.lab. in Toshiba Horikawa-cho Works, 72, Horikawa-cho. Saiwai-ku, Kawasaki 210, Japan
Michiyuki Sugihara
Affiliation:
Semicond. Group. Toshiba Corp., 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki 210, Japan.
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Abstract

The fabrication process of high current arsenic (As) ion implanted poly-silicon (Si) gate and source-drain (SD) electrode Si n-channel metal-oxide-semiconductor field-effect-transistor (MOSFET) was examined. Poly-Si film n-type doping was performed by using high current (typical current: 2mA) and relatively low acceleration voltage (40keV) As ion implantation technique (Lintott series 3). It was observed that high dose-As implanted poly-Si films as is show refractoriness against radical fluorine excited by microwave. Using GCA MANN4800 (m/c ID No.2, resist: OFPR) mask pattern printing technique, the high current As ion implantation technique and radical fluorine gas phase etching (Chemical dry etching: CDE) technique. the n-channel poly-Si gate (ps=∼L00ft/o) enhancement MOSFETs(ps-source-drain = =50n/o, SiO2 gate=380A) with off-leak-less were obtained on 3”Czochralski-grown 2Ωcm boron-doped p-type wafers (Osaka titanium). By the same process, a 8-bit single chip μ-processor with 26MHz full operation was performed.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 279: Symposium A – Beam-Solid Interactions–Fundamentals and Applications , 1992 , 313
Copyright
Copyright © Materials Research Society 1993

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