Hostname: page-component-7479d7b7d-jwnkl Total loading time: 0 Render date: 2024-07-13T17:43:15.945Z Has data issue: false hasContentIssue false
  • English
  • Français

Low-k Dielectric Integration Cost Modeling

Published online by Cambridge University Press:  15 February 2011

Ed Korczynski
Ed Korczynski*
Affiliation:
Solid State Technology, 1700 S. Winchester Blvd., Suite 201, Campbell, CA 95008, Tel: 408–370–4833, Fax: 408–370–9585, edk@pennwell.com
Get access

Abstract

The wide variety of low-k dielectric materials and processes for ULSI interconnection were sorted to create generic process flows. Average material and equipment costs were then used as inputs to a generic cost-per-wafer (CPW) model for dielectric deposition (not including the costs of dielectric CMP, metallization, or lithography). The model outputs are internally consistent, and useful for comparison of similar processes.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 476: Symposium N – Low-Dielectric Constant Materials III , 1997 , 177
Copyright
Copyright © Materials Research Society 1997

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1 The National Technology Roadmap for Semiconductors, Semiconductor Industry Association, 1994.Google Scholar
2 Seidel, T. and Zhao, B., Mater. Res. Soc. Symp. Proc., Vol.427, p. 3–16, 1996.Google Scholar
3 Zhao, B., Wang, S.-Q., Anderson, S., Lam, R., Fiebig, M., Vasudev, P. K., and Seidel, T. E., Mater. Res. Soc. Symp. Proc, Vol.427, p. 415–426, 1996.Google Scholar
4 Sugahara, G., Aoi, N., Kubo, M., Arai, K., Sawada, K., Proc of Dielectrics for ULSI Multilevel Interconnection Conference, p. 19–25, 1997.Google Scholar
5 Ramos, T., Roderick, K., Roth, R., Wallace, S., Hendricks, N., Rutherford, N., Drage, J., Wang, S.Q., and Smith, D.M., Proc of Dielectrics f or ULSI Multilevel Interconnection Conference, p. 106–113, 1997.Google Scholar
6 Jain, M. K., Taylor, K. J., Dixit, G. A., Lee, W. W., Ting, L. M., Shinn, G. B., Nag, S., Havemann, R. H., Luttmer, J. D., and Chang, M.,, Proc of VLSI Multilevel Interconnection Conference, p. 23–27, 1996.Google Scholar
7 McGahay, V., Acovic, A., Agarwala, B., Endicott, G., Nguyen, D., Shapiro, M., and Yankee, S., Proc of VLSI Multilevel Interconnection Conference, p. 116–118, 1996.Google Scholar
8 Robles, S., Vasquez, L., Eizenberg, M., and Maghadam, F., Proc. of Dielectrics for ULSI Multilevel Interconnection Conference, p. 26–33, 1997.Google Scholar
9 Matsubara, Y., Endo, K., Tatsumi, T., Ueno, H., Sugai, K., Horiuchi, T., Technical Digest of International Electron Devices Meeting, p. 369, 1996.Google Scholar