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Nanoscale Transistors: Physics and Materials

Published online by Cambridge University Press:  01 February 2011

Mark S. Lundstrom
Affiliation:
lundstro@purdue.edu, Purdue University, Electrical and Computer Engineering, EE Building, Room 310,, 465 Northwestern Ave., West Lafayette, IN, 47907-2035, United States
Kurtis D. Cantley
Affiliation:
kcantley@purdue.edu, Purdue University, Network for Computational Nanotechnology, Dept. of Electrical and Computer Engineering, West Lafayette, IN, 47907, United States
Himadri S. Pal
Affiliation:
hpal@purdue.edu, Purdue University, Network for Computational Nanotechnology, Dept. of Electrical and Computer Engineering, West Lafayette, IN, 47907, United States
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Abstract

We analyze a modern-day 65nm MOSFET technology to determine its electrical characteristics and intrinsic ballistic efficiency. Using that information, we then predict the performance of similar devices comprised of different materials, such as high-k gate dielectrics and III-V channel materials. The effects of series resistance are considered. Comparisons are made between the performance of these hypothetical devices and future generations of devices from the ITRS roadmap, including double-gate MOSFETs. We conclude that a Si channel device with a high-k gate dielectric and metal gate will outperform III-V channel materials for conventional CMOS applications, but will still not suffice in achieving long-term ITRS goals.

Type
Research Article
Copyright
Copyright © Materials Research Society 2007

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References

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