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Novel Wafer Dicing and Chip Thinning Technologies Realizing High Chip Strength

Published online by Cambridge University Press:  26 February 2011

Shinya Takyu
Affiliation:
taq@apd.tama.toshiba.co.jp, Toshiba Corporation Semiconductor Company, Advanced Packaging Process Engineering Group, 1, Komukai Toshiba-Cho, Saiwai-Ku, Kawasaki, 212-8583, Japan
Tetsuya Kurosawa
Affiliation:
kurosawa@apd.tama.toshiba.co.jp, TOSHIBA CORPORATION Semiconductor Company, Kawasaki, 212-8583, Japan
Noriko Shimizu
Affiliation:
noriko@apd.tama.toshiba.co.jp, TOSHIBA CORPORATION Semiconductor Company, Kawasaki, 212-8583, Japan
Susumu Harada
Affiliation:
harada@apd.tama.toshiba.co.jp, TOSHIBA CORPORATION Semiconductor Company, Kawasaki, 212-8583, Japan
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Abstract

As telecommunication equipment that supports high-level information networks is being made portable, the requirements for telecommunication equipment to be small and lightweight are becoming stricter. Thus, miniaturization of semiconductor devices is necessary, and wafer dicing and chip thinning technologies are important key technologies to achieve it. Wafers are thinned by mechanical in-feed grinding using a grindstone containing diamond particles, and wafers are divided by mechanical blade dicing using a diamond blade. However, mechanical processes using diamond grits leave damage such as chipping, saw mark or residual strain on chip surfaces; thus, chip strength decreases. At chip thicknesses of 50 to 200 μm, such damage has to be avoided.

In this study, the relationship between chip residual damage and chip strength is examined, and novel wafer dicing and thinning technologies that realize an average chip strength have increased from 253 MPa to 1903 MPa are described.

Type
Research Article
Copyright
Copyright © Materials Research Society 2007

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References

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