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The Roles of “3d/2d” and “3d/3d” Topography Simulators in Virtual Wafer Fabs

Published online by Cambridge University Press:  10 February 2011

T. S. Cale ,
T. P. Merchant  and
L. J. Borucki
T. S. Cale
Affiliation:
Dept. of Chemical Eng., Rensselaer Polytechnic Institute, Troy, NY 12180
T. P. Merchant
Affiliation:
Predictive Engineering Laboratory, Motorola, Inc. Mesa, AZ 85202
L. J. Borucki
Affiliation:
Predictive Engineering Laboratory, Motorola, Inc. Mesa, AZ 85202
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Abstract

After discussing topography simulation, we summarize two approaches used to move surfaces in topography simulators used in virtual semiconductor wafer fabs; “front tracking” and “level set”. Front tracking is presented for two dimensional (2d) surfaces, and a number of examples are shown to demonstrate the approach. The level set approach is presented for three dimensional (3d) surfaces, and examples are shown. Though either approach could be used in both 2d and 3d topography simulators, this is by and large the current usage. Transport and reaction submodels needed for physically based process simulations will continue to be developed using experiments performed on structures that are inherently 2d, combined with three dimensional 3d transport simulations; i.e., “3d/2d” simulations. Three dimensional device structures will be generated using “3d/3d” topography simulations, using robust codes. Plasma enhanced deposition of silicon dioxide from TEOS is used as an example of how 3d/2d and 3d/3d simulations are used.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 490: Symposium Q – Semiconductor Process & Device Performance Modeling , 1997 , 201
Copyright
Copyright © Materials Research Society 1998

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References

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