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The Selective Epitaxy of Silicon at Low Temperatures

Published online by Cambridge University Press:  22 February 2011

Jen-Chung Lou ,
William G. Oldham ,
Harry Kawayoshi  and
Peiching Ling
Jen-Chung Lou
Affiliation:
Electrical and Computer Sciences Department and Electronics Research Laboratory, University of California at Berkeley, CA
William G. Oldham
Affiliation:
Electrical and Computer Sciences Department and Electronics Research Laboratory, University of California at Berkeley, CA
Harry Kawayoshi
Affiliation:
Advanced Material Engineering Research, Sunnyvale, CA.
Peiching Ling
Affiliation:
Advanced Material Engineering Research, Sunnyvale, CA.
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Abstract

Low-temperature selective epitaxial growth (SEG) of silicon using a dichlorosilane-hydrogen mixture in an LPCVD hot-wall reactor has been discussed with respect to the wafer preparation and the deposition cycle. The surface morphology and the quality of epilayers are strongly affected by residual oxide islands at interface. A reduction of local growth rate near interfacial oxides is attributed to the dissolution of oxide at interface, and this reduction can lead to pits and textured features on the Si epitaxial surface. An ex-situ HF vapor or an HF dip with an in-situ small DCS 900°C prebake step can completely remove surface oxide prior to the deposition and achieve defect-free Si epilayers at the deposition temperatures of 850°C and 800°C. It is also found that fluorine atoms can play a major role in the removal of surface oxide.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 220: Symposium B – Silicon Molecular Beam Epitaxy , 1991 , 353
Copyright
Copyright © Materials Research Society 1991

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References

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