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Wafer Characterization of an Epi Reactor Using Sheet Resistance Mapping

Published online by Cambridge University Press:  28 February 2011

Walter H. Johnson ,
W. Andrew Keenan  and
Alan K. Smith
Walter H. Johnson
Affiliation:
Prometrix Corporation, 3255 Scott Blvd., Bldg. 2, Santa Clara, CA 95054
W. Andrew Keenan
Affiliation:
Prometrix Corporation, 3255 Scott Blvd., Bldg. 2, Santa Clara, CA 95054
Alan K. Smith
Affiliation:
Prometrix Corporation, 3255 Scott Blvd., Bldg. 2, Santa Clara, CA 95054
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Abstract

Sheet resistance mapping has become an indispensable tool in characterizing ion implanters for both integrated circuit manufacturers and equipment manufacturers. The sheet resistance mapping technique is now being extended into additional applications such as the characterization of metal deposition, CVD, and epitaxial silicon growth. This technique has become especially necessary with the advent of 150mm and 200mm wafers, where 5 or 9 site measurements cannot provide sufficient data essential for process control.

In order to optimize the performance of an epi reactor it is necessary to control and characterize the gas flows and temperature distributions inside the reactor. The control of these variables is essential for thickness and resistivity uniformity in epi layers. This paper describes the use of sheet resistance profiles and contour maps to study the resistivity and thickness uniformity variations in an epi reactor. The sheet resistance maps allow for control of the epi process without requiring data from other test sources.This ensures real time process control for production, as well as very rapid feedback for maintenance while doing equipment repair.

Type
Articles
Information
MRS Online Proceedings Library (OPL) , Volume 71: Symposium F – Materials Issues in Silicon Integrated Circuit Processing , 1986 , 113
Copyright
Copyright © Materials Research Society 1986

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References

[1] Keenan, W. A., Johnson, W. H. and Smith, A. K., “Production Monitoring of 200mm Wafer Processing”.Google Scholar
[2] Perloff, D. S., Gan, J. N. and Wahl, F. E., “Solid State Technology”, Vol. 24, No. 2, Feb 1981.Google Scholar
[3] Srinivasan, G. R., “Modeling and Applications of Silicon Epitaxy Silicon Processing”, ASTM STP 804, D. C. Gupta, Ed. American Society for Testing and Materials, 1983 pp 151–173.Google Scholar