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CMOS/SOS VLSI Technology

Published online by Cambridge University Press:  21 February 2011

Tai Sato ,
Jun Iwamura ,
Hiroyuki Tango  and
Katsuyuki Doi
Tai Sato
Affiliation:
Toshiba Corporation, Kawasaki, JAPAN
Jun Iwamura
Affiliation:
Toshiba Corporation, Kawasaki, JAPAN
Hiroyuki Tango
Affiliation:
Toshiba Corporation, Kawasaki, JAPAN
Katsuyuki Doi
Affiliation:
Toshiba Corporation, Kawasaki, JAPAN
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Abstract

CMOS is considered as a prospective technology in the VLSI era because of its low power consumption and high driving capability. While ordinary bulk silicon CMOS devices are inferior to SOS CMOS devices in chip area, operation speed and latch-up problem due to the need for isolation wells. SOS is an inherent good partner of the CMOS circuits owing to the simple and perfect isolation. SOS technology, however, has the problem of high wafer cost. Consequently, SOS technology is best applied to high performance logic devices. Latest results of 8k-gate CMOS/SOS gate array and 16×16bit multipliers show 0.87ns 2-NAND gate delay and 27ns multiplication time, respectively, which compete with ECL devices. Application of SOS devices down to 1μm is also promising for very high speed operation. A 78ps gate delay is achieved by double solid phase epitaxy and 1μm technology. INTRO

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 33: Symposium D – Comparison of Thin Film Transistor and SOI Technologies , 1984 , 25
Copyright
Copyright © Materials Research Society 1984

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References

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