Hostname: page-component-78c5997874-ndw9j Total loading time: 0 Render date: 2024-11-18T05:54:41.891Z Has data issue: false hasContentIssue false
  • English
  • Français

Current and Future Three-Dimensional LSI Integration Technology by “chip on chip”, “chip on wafer” and “wafer on wafer”

Published online by Cambridge University Press:  26 February 2011

Manabu Bonkohara ,
Makoto Motoyoshi ,
Kazutoshi Kamibayashi  and
Mitsumasa Koyanagi
Manabu Bonkohara
Affiliation:
bonkohara@zy-cube.com, ZyCube Co.,Ltd., Headquaters, Mitsuyoshi Bldg. 9F, 3-5-13 Nihonbashi,Chuo-ku, Japan, Tokyo, 103-0027, Japan, +81-3-6202-9690, +81-3-6202-9691
Makoto Motoyoshi
Affiliation:
makoto.motoyoshi@zy-cube.com, ZyCube Co., Ltd., Tokyo, 103-0027, Japan
Kazutoshi Kamibayashi
Affiliation:
k-kamibayashi@zy-cube.com, ZyCube Co., Ltd., Tokyo, 103-0027, Japan
Mitsumasa Koyanagi
Affiliation:
koyanagi@sd.mech.tohoku.ac.jp, Tohoku University, Sendai, 980-0845, Japan
Get access

Abstract

Recently the development of three dimensional LSI (3D-LSI) has been accelerated and its stage has changed from the research level or limited production level to the investigation level with a view to mass production. This paper describes the current and the future 3D-LSI technologies which we have considered and imagined. The current technology is taken our Chip Size Package (CSP) for sensor device, for instance. In the future technology, there are the five key technologies are described. And considering con and pro of the current 3D LSI stacked approach, such as CoC (Chip on Chip), CoW (Chip on Wafer) and WoW (Wafer on Wafer), We confirmed that CoW combined with Super-Smart-Stack (SSS™) technology will shorten the process time per chip at the same level as WoW approach and is effective to minimize process cost.

Keywords

packagingsensorself-assembly
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 970: Symposium Y – Enabling Technologies for 3-D Integration , 2006 , 0970-Y03-03
Copyright
Copyright © Materials Research Society 2007

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. Dennard, R. H., Gaensslen, F. H., Rideout, V. L., Bassous, E., and LeBlanc, A. R., IEEE J. Solid-State Circuits, SC-9, p.256 (1974)Google Scholar
2. Koyanagi, M., Extended Abst. 8th Symposium on Future Electron Devices, pp. 50–60, (1989)Google Scholar
3. Takata, H., Nakano, T., Yokoyama, S., Horiuchi, S., Itani, H., Tsukamoto, H., and Koyanagi, M., Extended Abst. 1991 Int'l Semiconductor Device Research Symposium, pp. 327–330, Dec (1991)Google Scholar
4. Koyanagi, M., Kurino, H., Matsumoto, T., Sakuma, K., Lee, K. W., Miyakawa, N., Itani, H., and, Tsukamoto, T., IEEE Int'l Workshop on Chip Package Co-Design, pp. 96–103 (1998)Google Scholar
5. Koyanagi, M., Kurino, H., Lee, K. W., Sakuma, K., Miyakawa, N., and Itani, H., IEEE MICRO, 18(4), pp.17–22 (1998)Google Scholar
6. Bonkohara, M., Proc. 6th Ann KGD Industrial Workshop, session II-3 (1999)Google Scholar
7. Kurino, H., Lee, K. W., Nakamura, T., Sakuma, K., Hashimoto, H., Park, K. T., Miyakawa, N., Shimazutsu, H., Kim, K. Y., Inamura, K., and Koyanagi, M., IEEE IEDM Technical Digest, pp.879–882 (1999)Google Scholar
8. Lee, K. W., Nakamura, T., Ono, T., Yamada, Y., Mizukusa, T., Hashimoto, H., Park, K. T., Kurino, H., and Koyanagi, M., IEEE IEDM Technical Digest, pp.165–168 (2002)Google Scholar
9. Ono, T., Mizukusa, T., Nakamura, T., Yamada, Y., Igarashi, Y., Morooka, T., Kurino, H., and Koyanagi, M., IEEE Cool Chip V, pp.186–193 (2002)Google Scholar
10. Gutmann, R.J., McMahon, J.J., Rao, S., Niklaus, F. and Lu, J.-Q., 2005 Int'l Wafer-Level Packaging Conference pp.122–127 (2005)Google Scholar
11. Motoyoshi, M., Kamibayashi, K., Bonkohara, M., and Koyanagi, M., Technical Digest on 3D Architecture for Semiconductor Integration and Packaging (2006)Google Scholar
12. Fukushima, T., Yamada, Y., Kikuchi, H., and Koyanagi, M., IEEE IEDM Technical Digest, pp.359–362 (2005)Google Scholar