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CVD Cu Process Development and Integration for sub-0.18 µm Devices

Published online by Cambridge University Press:  10 February 2011

Jiming Zhang
Affiliation:
Advanced Product Research and Development Lab, Motorola, Austin, TX, 78721
Dean Denning
Affiliation:
Advanced Product Research and Development Lab, Motorola, Austin, TX, 78721
Greg Braeckelmann
Affiliation:
Advanced Product Research and Development Lab, Motorola, Austin, TX, 78721
Greg Hamilton
Affiliation:
Advanced Product Research and Development Lab, Motorola, Austin, TX, 78721
J. J Lee
Affiliation:
Advanced Product Research and Development Lab, Motorola, Austin, TX, 78721
Ram Venkatraman
Affiliation:
Advanced Product Research and Development Lab, Motorola, Austin, TX, 78721
Bob Fiordalice
Affiliation:
Advanced Product Research and Development Lab, Motorola, Austin, TX, 78721
Elizabeth Weitzman
Affiliation:
Advanced Product Research and Development Lab, Motorola, Austin, TX, 78721
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Abstract

The advent of inlaid Cu interconnects has presented new challenges for the industry to fill high aspect ratio dual inlaid features. CVD Cu offers advantages for excellent step coverage and is a technique extendible for future generations of devices. We have developed a robust CVD Cu process and a CVD/PVD reflow integration scheme. In this paper, we present results of an extensive study on CVD Cu process development and integration. The effects of various precursors, carrier gases (H2, He and N2) and barrier layers including CVD TiN, PVD Ta, PVD TaN, PVD Ta-Si-N, and a hybrid barrier, on the CVD Cu film properties and device electrical properties are discussed. The extendibility and challenges of current CVD Cu processing will also be discussed.

Type
Research Article
Copyright
Copyright © Materials Research Society 1999

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