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Integration Challenges for Double-Gate MOSFET Technologies

Published online by Cambridge University Press:  15 March 2011

W.P. Maszara
W.P. Maszara*
Affiliation:
Strategic Technology Group, Advanced Micro Devices Sunnyvale, CA 94088-3453
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Abstract

Device modeling data and some early experiments suggests that fully depleted MOSFET devices where channel is controlled by two opposing gates or one gate that surrounds most or the entire channel, will provide better scaling than the classic devices with one gate on one side of the channel. However, formation of such devices requires complex, non-conventional and sometimes exotic geometry and processing, ranging from wafer bonding to selective lateral ‘tunnel’ epitaxy, to selectively wet-etched channels with triangular cross-section. Classic single-gate transistors have been recently demonstrated with reasonable performance at 20-15 nm of physical gate length. Double-gate transistors with their process integration complexity will likely become a viable alternative for smaller geometries. This paper will discuss various approaches to realization of those multi-gate fully depleted devices and their process integration challenges for sub-15 nm gates.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 686: Symposium A – Materials Issues in Novel Si-Based Technology , 2001 , A2.5
Copyright
Copyright © Materials Research Society 2002

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