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A Process for 0.5 Micron CMOS Gate Definition

Published online by Cambridge University Press:  25 February 2011

D. Stanasolovich ,
S. Katz ,
S. Schnur ,
D. Danner  and
L. K. Wang
D. Stanasolovich
Affiliation:
IBM Federal Systems Division 9500 Godwin Drive, Manassas, VA 22110 (703) 367-1600
S. Katz
Affiliation:
IBM Federal Systems Division 9500 Godwin Drive, Manassas, VA 22110 (703) 367-1600
S. Schnur
Affiliation:
IBM Federal Systems Division 9500 Godwin Drive, Manassas, VA 22110 (703) 367-1600
D. Danner
Affiliation:
IBM T.J. Watson Research Center P.O. Box 218, Yorktown Heights, N.Y. 10598 (914) 945-3736
L. K. Wang
Affiliation:
IBM T.J. Watson Research Center P.O. Box 218, Yorktown Heights, N.Y. 10598 (914) 945-3736
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Abstract

A RIE process has been developed for the etching of 0.5 μm CMOS Polysilicon gates defined using both E-Beam direct writing and sub-micron optical lithography. Profile control and selectivity were enhanced by using a two-step pattern transfer process wherein the Photoresist mask was used to define a thin Silicon Nitride layer which was subsequently used to define the underlying Polysilicon gate electrode. High etch selectivity to both the Silicon Nitride mask and the thin gate oxide was achieved using a Cl2 plasma chemistry after a BCl3 initiation step. The effect of BCl3 initiation on the poly profile and the effect of loading on profile and selectivity will be presented.

Type
Articles
Information
MRS Online Proceedings Library (OPL) , Volume 76: Symposium C – Science and Technology of Microfabrication , 1986 , 271
Copyright
Copyright © Materials Research Society 1987

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References

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