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Reliability Issues with Mixed-Signal CMOS Technology

Published online by Cambridge University Press:  15 February 2011

Rajeeva Lahri ,
Hung-Sheng Chen ,
Ji Zhao ,
Kamesh Gadepally  and
C.S. Teng
Rajeeva Lahri
Affiliation:
CMOS Technology Development, National Semiconductor Corp, Santa Clara, CA 95052
Hung-Sheng Chen
Affiliation:
CMOS Technology Development, National Semiconductor Corp, Santa Clara, CA 95052
Ji Zhao
Affiliation:
CMOS Technology Development, National Semiconductor Corp, Santa Clara, CA 95052
Kamesh Gadepally
Affiliation:
CMOS Technology Development, National Semiconductor Corp, Santa Clara, CA 95052
C.S. Teng
Affiliation:
CMOS Technology Development, National Semiconductor Corp, Santa Clara, CA 95052
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Abstract

In a Mixed-Signal IC, both digital and analog circuits exist on the same chip. Analog circuit blocks require technology attributes like precise device matching, low parametric drifts and low noise. These requirements raise additional reliability issues, over and above the reliability concerns associated with digital circuits. CMOS device reliability for mixed-signal technologies can be enhanced by modifying device architecture and improving gate oxide integrity. Interconnect metallurgy plays an important role in determining electromigration related contact/via resistance change which may impact matching of devices and resistor pairs. Appropriate source/drain engineering, device design and utilizing nitrided gate oxide has been shown to produce extremely stable devices. This article will cover process architecture and material issues related with device stability and interconnect metallurgy issues related with contact/via stability, especially with W-Plugs.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 391: Symposium T – Materials Reliability in Microelectronics V , 1995 , 47
Copyright
Copyright © Materials Research Society 1995

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References

1 J. Huang, H., Liu, Z. H., Jeng, M. C., Ko, P. K., and Hu, C., “A physical model for MOSFET output resistance,” IEDM, p. 569, 1992.Google Scholar
2 Su, L. T., Yasaitis, J. A., and Antoniadis, D. A., “A high-performance scalable submicron MOSFET for mixed analog/digital applications”, IEDM, p. 367, 1991.Google Scholar
3 Chen, H. S., Zhao, J., Teng, C. S., Moberly, L., and Lahri, R., “Submicron Large-Angle-Tilt Implanted Drain Technology for Mixed-Signal Applications,” IEDM, p. 91, 1994.Google Scholar
4 Hori, T. and Kurimoto, K., “Deep-submicrometer large-angle-tilt implanted drain (LATID) technology,” IEEE Trans. Electron Devices, p. 2312, 1992.Google Scholar
5 Sodini, C. G., Wong, S. S., and Ko, P. K., “A framework to evaluate technology and device design enhancements for MOS integrated circuits,” IEEE J. of solid-state circuits, p. 118, 1989.Google Scholar
6 Chung, J. E., Quader, K. N., Sodini, C. G., Ko, P. K., and Hu, C., “The effect of hot-electron degradation on analog MOSFET performance,” IEDM, p. 553, 1990.Google Scholar
7 Rakkhit, R. et al, “Process induced oxide damage and its implications to device reliability of submicron transistors,” 31st Ann. Pro., IRPS, p. 293, 1993.Google Scholar
8 Fang, S. et al, “A new model for thin oxide degradation from wafer charging in plasma etching,” IEDM tech. Dig., p. 61, 1992.Google Scholar
9 Hu, C., Zhao, J., Li, G. P., Liu, P., Worley, E., White, J., and R, Kjar, “The effects of plasma etching induced gate oxide degradation on MOSFET’s 1/f noise,” IEEE Electron Device Lett. vol. 16, No. 2, pp. 61-63.Google Scholar
10 Black, J. R., IEEE Trans. Electron Devices ED-16 (1969) p.338.Google Scholar
11 Gadepally, K., Geha, S., Myers, E., and Michael, Thomas, E., “Electromigration Properties and their Correlation to the Physical Characteristics of Multilevel Metallizations”, Pg 301, Vol. 338 MRS Proceedings, 1994.Google Scholar
12 Kamesh, Gadepally, Padala, Krishna Reddy, Siew, Hiew, Richard, Merrill, Rajeeva, Lahri, and Madan, Biswal, “Effect Of, TiW As Adhesion Layer, And, Underlying Metal On Electromigration Characteristics of Tungsten Via Plugs”, MRS Proceedings, 1993.Google Scholar
13 Enver, A., and Clement, J. J., “Finite Element Numerical Modeling of Currents in VLSI Interconnects”, VMIC Conference Proceedings, Pg 149, 1990.Google Scholar
14 Anant, Sabnis, G., “VLSI Reliability - VLSI Electronics Microstructure Science ” Vol 22. pg 66, Academic Press, 1990.Google Scholar
15 Turner, T. and Wendel, K., Proceedings of the 23rd IEEE IRPS, 1985, pp 142–147.Google Scholar
16 Lytle, S. A. and Oates, A.S., “The effect of stress-induced voiding on electromigration”, J. Appl.Phys. 71 (1), 1 January 1992 pp. 174 178.Google Scholar