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Solid Phase Epitaxial Recrystallization of Sos, with Applications to Submicrometer Cmos and Bipolar Devices

Published online by Cambridge University Press:  28 February 2011

P.K. Vasudev
P.K. Vasudev*
Affiliation:
Hughes Research Laboratories, Malibu, CA 90265
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Abstract

CMOS/SOS devices and circuits were fabricated in 0.3-µm-thick epitaxial silicon-on-sapphire (SOS) films. Two solid phase epitaxial recrystallization techniques (DSPE* and SPEAR**) reduced the total microtwin concentrations in the Si layers more than ten- fold, while increasing electron and hole inversion layer mobilities between 30 and 45%. Leakage currents were substantially reduced in all SPEAR devices and in n-channel DSPE transistors, with some increase observed for p-channel DSPE devices. Drive currents and subthresholds slopes also showed significant improvement in both n- and p-devices. Propagation delays below 75 ps were obtained for CMOS/SOS inverters with Lef = 0.5 µm. The application of DSPE and SPEAR techniques to 0.3-µm SOS films will extend the scaling of CMOS/SOS to circuits with very large scale integration (VLSI) complexity.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 53 , 1985 , 121
Copyright
Copyright © Materials Research Society 1986

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References

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