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Structure and Process Parameter Optimization for Sub-10nm Gate Length Fully Depleted N-Type SOI MOSFETs by TCAD Modeling and Simulation

Published online by Cambridge University Press:  01 February 2011

Yawei Jin ,
Lei Ma ,
Chang Zeng ,
Krishnanshu Dandu  and
Doug William Barlage
Yawei Jin
Affiliation:
yjin3@ncsu.edu, North Carolina State University, Electrical and Computer Engineering, 2828 Avent Ferry Rd. Apt. 202,, Raleigh, NC, 27606, Raleigh, North Carolina, 27606, United States, 919-946-3039
Lei Ma
Affiliation:
lma@ncsu.edu, North Carolina State University, ECE, Raleigh, NC, 27695, United States
Chang Zeng
Affiliation:
czeng@ncsu.edu, North Carolina State University, ECE, Raleigh, NC, 27695, United States
Krishnanshu Dandu
Affiliation:
kdandu@ncsu.edu, North Carolina State University, ECE, Raleigh, NC, 27695, United States
Doug William Barlage
Affiliation:
dwbarlag@ncsu.edu, North Carolina State University, ECE, Raleigh, NC, 27695, United States
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Abstract

According to most recent 2004 International Technology Roadmap for Semiconductor (2004 ITRS), the high performance (HP) MOSFET physical gate length will be scaled to 9nm (22nm technology node) in 2016. We investigate the manufacturability of this sub-10nm gate length fully depleted SOI MOSFET by TCAD simulation. The commercial device simulator ISE TCAD is used. While it is impractical for experiments currently, this study can be used to project performance goals for aggressively scaled devices. In this paper, we will optimize different structure and process parameters at this gate length, such as body thickness, oxide thickness, spacer width, source/drain doping concentration, source/drain doping abruptness, channel doping concentration etc. The sensitivity of device electrical parameters, such as Ion, Ioff, DIBL, Sub-threshold Swing, threshold voltage, trans-conductance etc, to physical variations will be considered. The main objective of this study is to identify the key design issues for sub-10nm gate length Silicon based fully depleted MOSFET at the end of the ITRS. The paper will present the final optimized device structure and optimized performance will be reported.

Keywords

simulationSinanoscale
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 913: Symposium D – Transistor Scaling – Methods, Materials and Modeling , 2006 , 0913-D01-10
Copyright
Copyright © Materials Research Society 2006

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