Hostname: page-component-78c5997874-4rdpn Total loading time: 0 Render date: 2024-11-19T03:31:49.096Z Has data issue: false hasContentIssue false

Three Dimensional Interconnect Stress Modeling for Back EndProcess

Published online by Cambridge University Press:  17 March 2011

Xiaopeng Xu
Affiliation:
TCAD R&D, Synopsys, Inc. 700 E. Middlefield Rd, Mountain View, CA 94043, USA
Victor Moroz
Affiliation:
TCAD R&D, Synopsys, Inc. 700 E. Middlefield Rd, Mountain View, CA 94043, USA
Get access

Abstract

A process oriented approach is demonstrated for modeling the stressevolution during the entire back end process flow. No ad hoc assumptions regarding stress states are made for layerdeposition and etching. Intrinsic stresses from material formation, thermalmismatch stresses from temperature ramps, stress relaxation due to viscousdeformation, and stress profile redistribution upon deposition and etchingare all considered at each process. Parametric studies are carried out toexamine the effects of viscous flow, material selection and layoutvariations. It is found that the viscous flow of the passivation anddielectric materials have large impact on stress evolution. A TCAD assisteddesign approach is suggested for lowering stress levels of critical stresscomponents. The implications of the stress modeling results on reliabilityissues like stress-triggered void formation are discussed.

Type
Research Article
Copyright
Copyright © Materials Research Society 2004

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1. Shen, Y.-L., “Thermo-Mechanical Modeling of Metal Interconnects in Microelectronic Devices”, in Recent Research Developments in Materials Science IV, Chapter 6, pp. 125155, Research Signpost, 2003.Google Scholar
2. Hierlemann, M. et al. , “Impact of Mechanical Stress on BEOL Reliability, Enhanced Understanding by TCAD Simulation”, ChiPPs meeting, Oct. 13-17, 2002, Prague.Google Scholar
3. Lee, J. and Mack, A. S., IEEE Trans. Semi. Manufacture, 11, 458 (1998).CrossRefGoogle Scholar
4. Yang, K., Waeterloos, J. J., Im, J., and Mills, M. E., “Sequential Process Modeling for Determining Process-Induced Thermal Stress in Advanced Cu/Low-k Interconnects”, MRS Spring meeting, 2003, San Francisco.CrossRefGoogle Scholar
5. Senez, V., Collard, D., Ferreira, P., and Baccus, B., IEEE Trans. Electron Dev., 43, 720 (1996).CrossRefGoogle Scholar
6.Taurus Process Reference Manual, version 2003.12, Synopsys, Inc., Mountain View, CA, USA.Google Scholar