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Three Dimensional Interconnect Stress Modeling for Back End Process

Published online by Cambridge University Press:  17 March 2011

Xiaopeng Xu  and
Victor Moroz
Xiaopeng Xu
Affiliation:
TCAD R&D, Synopsys, Inc. 700 E. Middlefield Rd, Mountain View, CA 94043, USA
Victor Moroz
Affiliation:
TCAD R&D, Synopsys, Inc. 700 E. Middlefield Rd, Mountain View, CA 94043, USA
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Abstract

A process oriented approach is demonstrated for modeling the stress evolution during the entire back end process flow. No ad hoc assumptions regarding stress states are made for layer deposition and etching. Intrinsic stresses from material formation, thermal mismatch stresses from temperature ramps, stress relaxation due to viscous deformation, and stress profile redistribution upon deposition and etching are all considered at each process. Parametric studies are carried out to examine the effects of viscous flow, material selection and layout variations. It is found that the viscous flow of the passivation and dielectric materials have large impact on stress evolution. A TCAD assisted design approach is suggested for lowering stress levels of critical stress components. The implications of the stress modeling results on reliability issues like stress-triggered void formation are discussed.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 812: Symposium F – Materials, Technology and Reliability for Advanced Interconnects and Low-k Dielectrics-2004 , 2004 , F6.25
Copyright
Copyright © Materials Research Society 2004

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