Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgements
- Chapter 1 Introduction to Microelectronics
- Chapter 2 From Algorithms to Architectures
- Chapter 3 Functional Verification
- Chapter 4 Modelling Hardware with VHDL
- Chapter 5 The Case for Synchronous Design
- Chapter 6 Clocking of Synchronous Circuits
- Chapter 7 Acquisition of Asynchronous Data
- Chapter 8 Gate- and Transistor-Level Design
- Chapter 9 Energy Efficiency and Heat Removal
- Chapter 10 Signal Integrity
- Chapter 11 Physical Design
- Chapter 12 Design Verification
- Chapter 13 VLSI Economics and Project Management
- Chapter 14 A Primer on CMOS Technology
- Chapter 15 Outlook
- Appendix A Elementary Digital Electronics
- Appendix B Finite State Machines
- Appendix C VLSI Designer's Checklist
- Appendix D Symbols and constants
- References
- Index
- Plate section
Appendix C - VLSI Designer's Checklist
- Frontmatter
- Contents
- Preface
- Acknowledgements
- Chapter 1 Introduction to Microelectronics
- Chapter 2 From Algorithms to Architectures
- Chapter 3 Functional Verification
- Chapter 4 Modelling Hardware with VHDL
- Chapter 5 The Case for Synchronous Design
- Chapter 6 Clocking of Synchronous Circuits
- Chapter 7 Acquisition of Asynchronous Data
- Chapter 8 Gate- and Transistor-Level Design
- Chapter 9 Energy Efficiency and Heat Removal
- Chapter 10 Signal Integrity
- Chapter 11 Physical Design
- Chapter 12 Design Verification
- Chapter 13 VLSI Economics and Project Management
- Chapter 14 A Primer on CMOS Technology
- Chapter 15 Outlook
- Appendix A Elementary Digital Electronics
- Appendix B Finite State Machines
- Appendix C VLSI Designer's Checklist
- Appendix D Symbols and constants
- References
- Index
- Plate section
Summary
Design data sanity
Are design data fully consistent? Have all design modifications always been propagated? Has the design data base never been tampered with (e.g. using a text or stream editor)?
Are you sure that no source data such as HDL specifications, schematics, netlists, macrocell generator instructions, and the like have been modified after physical design was begun?
Have all verification steps (simulation, ERC, timing verification, DRC, LVS, etc.) been carried out on the most recent version of the design?
Do the cell libraries and/or transistor models being used indeed apply to the fabrication process and the operating conditions targetted?
Have all library elements been fully characterized? Beware of “0” or other default entries sometimes entered by library developers for properties (such as area, propagation delay, power dissipation, etc.) the numerical values of which have not yet been established.
Pre-synthesis design verification
Is a bit-true and cycle-true behavioral model available (in HDL, C, or Matlab)? Has this circuit model been thoroughly tested in system-level simulations? Have the system designers checked and accepted the results so obtained?
Do the logic gauges used in simulating a behavioral model systematically cover all modes and conditions under which the circuit is going to operate?
Do the logic gauges also address uncommon situations, such as exceptional control flows, corrupt input data, numeric exceptions (e.g. divide by zero), overflows and underflows, truncation and rounding, data values outside of their habitual range, non-rational frequency ratios, and the like?
- Type
- Chapter
- Information
- Digital Integrated Circuit DesignFrom VLSI Architectures to CMOS Fabrication, pp. 794 - 803Publisher: Cambridge University PressPrint publication year: 2008