Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgements
- Chapter 1 Introduction to Microelectronics
- Chapter 2 From Algorithms to Architectures
- Chapter 3 Functional Verification
- Chapter 4 Modelling Hardware with VHDL
- Chapter 5 The Case for Synchronous Design
- Chapter 6 Clocking of Synchronous Circuits
- Chapter 7 Acquisition of Asynchronous Data
- Chapter 8 Gate- and Transistor-Level Design
- Chapter 9 Energy Efficiency and Heat Removal
- Chapter 10 Signal Integrity
- Chapter 11 Physical Design
- Chapter 12 Design Verification
- Chapter 13 VLSI Economics and Project Management
- Chapter 14 A Primer on CMOS Technology
- Chapter 15 Outlook
- Appendix A Elementary Digital Electronics
- Appendix B Finite State Machines
- Appendix C VLSI Designer's Checklist
- Appendix D Symbols and constants
- References
- Index
- Plate section
Chapter 12 - Design Verification
- Frontmatter
- Contents
- Preface
- Acknowledgements
- Chapter 1 Introduction to Microelectronics
- Chapter 2 From Algorithms to Architectures
- Chapter 3 Functional Verification
- Chapter 4 Modelling Hardware with VHDL
- Chapter 5 The Case for Synchronous Design
- Chapter 6 Clocking of Synchronous Circuits
- Chapter 7 Acquisition of Asynchronous Data
- Chapter 8 Gate- and Transistor-Level Design
- Chapter 9 Energy Efficiency and Heat Removal
- Chapter 10 Signal Integrity
- Chapter 11 Physical Design
- Chapter 12 Design Verification
- Chapter 13 VLSI Economics and Project Management
- Chapter 14 A Primer on CMOS Technology
- Chapter 15 Outlook
- Appendix A Elementary Digital Electronics
- Appendix B Finite State Machines
- Appendix C VLSI Designer's Checklist
- Appendix D Symbols and constants
- References
- Index
- Plate section
Summary
While much engineering effort in a VLSI design project goes into checking whether the HDL models developed do indeed capture the desired functionality, this does not suffice to make sure the design data submitted to fabrication are correct. Design flaws may also creep in during netlist synthesis and layout preparation. The extra checks required to uncover such problems and the EDA tools available to do so are the subject of this chapter. Section 12.1 is concerned with locating timing problems while section 12.2 analyzes the accuracy of the timing models being used. Electrical rule check (ERC) and other static design verification techniques are the subject of section 12.3. Section 12.4, finally, addresses post-layout design verification.
Uncovering timing problems
As underlined in earlier chapters of this text, getting the timing right is vital for making VLSI circuits work as intended; catching potential timing problems is thus very important indeed. One is easily tempted to accept an error-free simulation run as a proof for a workable design, yet this is not so. We will first demonstrate why before introducing a more effective approach in section 12.1.2.
What does simulation tell us about timing problems?
Abstracting from the fine points that make up the differences between the various clocking disciplines, almost all timing-related difficulties that may occur in a synchronous (sub)system can be attributed to one or more of the causes listed below.
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- Digital Integrated Circuit DesignFrom VLSI Architectures to CMOS Fabrication, pp. 581 - 614Publisher: Cambridge University PressPrint publication year: 2008