Capacitance contribution from interface states

Interface states will give rise to a capacitance adding to that associated with the semiconductor of the MOS combination. The reason is the charge exchange taking place between captured carriers at the interface and the semiconductor energy bands. Since the emission and capture at the interface states take place by thermal processes, determined by the emission rates, en, and the capture rates, cn = vthσn, with the corresponding quantities for holes, a certain time delay occurs before the capacitance reaches a value given by thermal equilibrium in the semiconductor. As will be demonstrated in this chapter, these events can be used to determine capture properties and energy distribution functions, Dit(ΔG), for electrons and holes, where ΔG is the free energy distance between one of the bands and the interface trap level (ΔGn for electrons and ΔGp for holes).

We consider a conduction band diagram for a MOS interface with an n-type semiconductor biased into weak accumulation, such that a downward bending and an accumulation of electrons takes place at the interface, as shown in Fig. 6.1(a). A weak AC voltage (about 10–20 mV) is added to the DC giving rise to the band bending. The occupation of interface states at thermal equilibrium is determined by the position of the Fermi level, μ, in the semiconductor bulk. An interface state, positioned at energy level GT = μ, will be occupied with a probability of ½ as described by Eq. (4.41).