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  3. Advanced Model Order Reduction Techniques in VLSI Design
  • Cited by 91
      • Sheldon Tan, University of California, Riverside, Lei He, University of California, Los Angeles
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    • Publisher:
      Cambridge University Press
      Publication date:
      19 January 2010
      31 May 2007
      ISBN:
      9780511541117
      9780521865814
      9781107411548
      DOI:
      https://doi.org/10.1017/CBO9780511541117
      Dimensions:
      (247 x 174 mm)
      Weight & Pages:
      0.68kg, 260 Pages
      Dimensions:
      (244 x 170 mm)
      Weight & Pages:
      0.42kg, 260 Pages
      • Subjects:
      Engineering, Circuits and Systems, Computer Engineering
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    • Selected: Digital
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    Subjects:
    Engineering, Circuits and Systems, Computer Engineering
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    Book description

    Model order reduction (MOR) techniques reduce the complexity of VLSI designs, paving the way to higher operating speeds and smaller feature sizes. This book presents a systematic introduction to, and treatment of, the key MOR methods employed in general linear circuits, using real-world examples to illustrate the advantages and disadvantages of each algorithm. Following a review of traditional projection-based techniques, coverage progresses to more advanced MOR methods for VLSI design, including HMOR, passive truncated balanced realization (TBR) methods, efficient inductance modeling via the VPEC model, and structure-preserving MOR techniques. Where possible, numerical methods are approached from the CAD engineer's perspective, avoiding complex mathematics and allowing the reader to take on real design problems and develop more effective tools. With practical examples and over 100 illustrations, this book is suitable for researchers and graduate students of electrical and computer engineering, as well as practitioners working in the VLSI design industry.

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