In this chapter we shall turn our attention to the implementation of encoders and decoders. Elementary encoders and decoders will be based on shift-register circuits; more advanced encoders and decoders will be based on hardware circuits and software routines for Galois-field arithmetic.

Digital logic circuits can be organized easily into shift-register circuits that mimic the cyclic shifts and polynomial arithmetic used in the description of cyclic codes. Consequently, the structure of cyclic codes is closely related to the structure of shift-register circuits. These circuits are particularly well-suited to the implementation of many encoding and decoding procedures and often take the form of filters. In fact, many algorithms for decoding simple cyclic codes can be described most easily by using the symbolism of shift-register circuits. Studying such decoders for simple codes is worthwhile for its own sake, but it is also a good way to build up the insights and techniques that will be useful for designing decoders for large codes.

Logic circuits for finite-field arithmetic

Logic circuits are easily designed to execute the arithmetic of Galois fields, especially if q is a power of 2. We shall need circuit elements to store field elements and to perform arithmetic in the finite field.

A shift register, as shown in Figure 8.1, is a string of storage devices called stages. Each stage contains one element of GF(q). The symbol contained in each storage device is displayed on an output line leaving that stage.