Book contents
- Frontmatter
- Abstract
- Preface
- Contents
- List of Figures
- List of Plates
- List of Tables
- List of Algorithms
- Glossary of Terms
- 1 Introduction
- 2 Two-Dimensional Chip Design
- 3 Three-Dimensional Chip Technology
- 4 Three-Dimensional Circuit Topology
- 5 Three-Dimensional Cell Tessellation
- 6 Three-Dimensional Abutment System
- 7 Abutment System Configuration
- 8 Abutment System Evaluation
- 9 Conclusions
- A Layout Editor Configuration
- B Layout System Data Structures
- C Cell Description Rules
- D Circuits
- References
- Index
Abstract
Published online by Cambridge University Press: 05 May 2010
- Frontmatter
- Abstract
- Preface
- Contents
- List of Figures
- List of Plates
- List of Tables
- List of Algorithms
- Glossary of Terms
- 1 Introduction
- 2 Two-Dimensional Chip Design
- 3 Three-Dimensional Chip Technology
- 4 Three-Dimensional Circuit Topology
- 5 Three-Dimensional Cell Tessellation
- 6 Three-Dimensional Abutment System
- 7 Abutment System Configuration
- 8 Abutment System Evaluation
- 9 Conclusions
- A Layout Editor Configuration
- B Layout System Data Structures
- C Cell Description Rules
- D Circuits
- References
- Index
Summary
Some recent developments in semiconductor process technology have made possible the construction of three-dimensional integrated circuits. Unlike other technological developments in two-dimensional integration, these circuits present a new and inherently richer connection topology. This offers the potential for improved layout in terms of increased density and reduced interconnect length. These circuits will be difficult and expensive to manufacture, at least in the short term, and the scale of the improvement in layout is not apparent. This dissertation presents a discussion of layout and design for three-dimensional integrated circuits.
A number of materials and techniques can be used in the manufacture of such circuits. This choice has a profound bearing on the topology of circuit layout. A classification relating process technology to layout topology is developed and illustrated with the design of a number of circuits. A layout system is presented as the vehicle for a series of experiments in three-dimensional layout. It is shown that the system can be constrained to perform circuit layout in a number of topologies in the classification.
Finally, some attempt to quantify the benefits of three-dimensional layout is made. The layout model is calibrated by designing examples of basic circuit elements.
- Type
- Chapter
- Information
- Three-Dimensional Integrated Circuit Layout , pp. vii - viiiPublisher: Cambridge University PressPrint publication year: 1991