Book contents
- Frontmatter
- Abstract
- Preface
- Contents
- List of Figures
- List of Plates
- List of Tables
- List of Algorithms
- Glossary of Terms
- 1 Introduction
- 2 Two-Dimensional Chip Design
- 3 Three-Dimensional Chip Technology
- 4 Three-Dimensional Circuit Topology
- 5 Three-Dimensional Cell Tessellation
- 6 Three-Dimensional Abutment System
- 7 Abutment System Configuration
- 8 Abutment System Evaluation
- 9 Conclusions
- A Layout Editor Configuration
- B Layout System Data Structures
- C Cell Description Rules
- D Circuits
- References
- Index
8 - Abutment System Evaluation
Published online by Cambridge University Press: 05 May 2010
- Frontmatter
- Abstract
- Preface
- Contents
- List of Figures
- List of Plates
- List of Tables
- List of Algorithms
- Glossary of Terms
- 1 Introduction
- 2 Two-Dimensional Chip Design
- 3 Three-Dimensional Chip Technology
- 4 Three-Dimensional Circuit Topology
- 5 Three-Dimensional Cell Tessellation
- 6 Three-Dimensional Abutment System
- 7 Abutment System Configuration
- 8 Abutment System Evaluation
- 9 Conclusions
- A Layout Editor Configuration
- B Layout System Data Structures
- C Cell Description Rules
- D Circuits
- References
- Index
Summary
Introduction
Aims
The previous chapter presented a preliminary set of experiments which were designed to examine the performance of different operating configurations of the layout system. The experiments were confined to a single three-dimensional layout environment based on a fixed number of layers of cuboid cells with one connection per face. This chapter describes a second set of experiments which build on the above findings and which explicitly investigate the properties of three-dimensional layouts. The questions addressed are:
How does cell library design affect layout?
How does the separation between layers of cells affect layout?
How many layers of cells offer improvement?
How do the results compare with two-dimensional layout?
In the first experiment, a comparison is made between layouts using different libraries of cells. The cell design exercise presented in chapter five is revisited and the design of more complex cells with greater active connection capability is presented. The dimensions of these cells are used to make absolute comparisons between layouts using different libraries of cells. The second experiment investigates a technological advantage of three-dimensional integration which is the potentially small separation between device layers. The effect of reduced vertical separation on the quality of layout is examined.
A key question about three-dimensional layout concerns the benefit of using more layers of active cells. This is the subject of the third experiment, which includes an examination of how the layout system behaves with a single active layer, and how additional wiring layers are utilised.
- Type
- Chapter
- Information
- Three-Dimensional Integrated Circuit Layout , pp. 145 - 168Publisher: Cambridge University PressPrint publication year: 1991