Book contents
- Frontmatter
- Abstract
- Preface
- Contents
- List of Figures
- List of Plates
- List of Tables
- List of Algorithms
- Glossary of Terms
- 1 Introduction
- 2 Two-Dimensional Chip Design
- 3 Three-Dimensional Chip Technology
- 4 Three-Dimensional Circuit Topology
- 5 Three-Dimensional Cell Tessellation
- 6 Three-Dimensional Abutment System
- 7 Abutment System Configuration
- 8 Abutment System Evaluation
- 9 Conclusions
- A Layout Editor Configuration
- B Layout System Data Structures
- C Cell Description Rules
- D Circuits
- References
- Index
A - Layout Editor Configuration
Published online by Cambridge University Press: 05 May 2010
- Frontmatter
- Abstract
- Preface
- Contents
- List of Figures
- List of Plates
- List of Tables
- List of Algorithms
- Glossary of Terms
- 1 Introduction
- 2 Two-Dimensional Chip Design
- 3 Three-Dimensional Chip Technology
- 4 Three-Dimensional Circuit Topology
- 5 Three-Dimensional Cell Tessellation
- 6 Three-Dimensional Abutment System
- 7 Abutment System Configuration
- 8 Abutment System Evaluation
- 9 Conclusions
- A Layout Editor Configuration
- B Layout System Data Structures
- C Cell Description Rules
- D Circuits
- References
- Index
Summary
The configuration file of the Qudos Layout Editor describes routable layers such as metal and polysilicon and via layers which describe the relationship between routable layers. For three-dimensional CMOS SOI design rules, a vertical connection is described by a metal layer with no contact overlap. The contact overlap will be provided on the planar metal layer to which the vertical metal layer connects. The structure of the layers is shown in Figure A.1. The layer ‘Dummy’ avoids a limitation of the system, and is introduced to maintain full design rule checking. The corresponding configuration file is included below.
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- Information
- Three-Dimensional Integrated Circuit Layout , pp. 177 - 182Publisher: Cambridge University PressPrint publication year: 1991