Hostname: page-component-78c5997874-8bhkd Total loading time: 0 Render date: 2024-11-09T05:03:39.713Z Has data issue: false hasContentIssue false
  • English
  • Français

200. mm Silicon Wafer-to-Wafer Bonding with Thin Ti Layer under BEOL-Compatible Process Conditions

Published online by Cambridge University Press:  01 February 2011

J. Yu ,
J. J. McMahon ,
J.-Q. Lu  and
R. J. Gutmann
J. Yu
Affiliation:
Focus Center – New York, Rensselaer: Interconnections for Hyperintegration, Rensselaer Polytechnic Institute, Troy, New York 12180
J. J. McMahon
Affiliation:
Focus Center – New York, Rensselaer: Interconnections for Hyperintegration, Rensselaer Polytechnic Institute, Troy, New York 12180
J.-Q. Lu
Affiliation:
Focus Center – New York, Rensselaer: Interconnections for Hyperintegration, Rensselaer Polytechnic Institute, Troy, New York 12180
R. J. Gutmann
Affiliation:
Focus Center – New York, Rensselaer: Interconnections for Hyperintegration, Rensselaer Polytechnic Institute, Troy, New York 12180
Get access

Abstract

Wafer level monolithic three-dimensional (3D) integration is an emerging technology to realize enhanced performance and functionality with reduced form-factor and manufacturing cost. The cornerstone for this 3D processing technology is full-wafer bonding under back-end-of-the-line (BEOL) compatible process conditions. For the first time to our knowledge, we demonstrate nearly void-free 200 mm wafer-to-wafer bonding with an ultra-thin Ti adhesive coating, annealed at BEOL-compatible temperature (400 °C) in vacuum with external pressure applied. Mechanical integrity test showed that bonded wafer pair survived after a stringent three-step thinning process (grinding/polishing/wet-etching) with complete removal of top Si wafer, while allowing optical inspection of bonding interface. Mechanisms contributing to the strong bonding at Ti/Si interface are briefly discussed.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 843: Symposium T – Surface Engineering-Fundamentals and Applications , 2004 , T7.5
Copyright
Copyright © Materials Research Society 2005

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. Morrow, P., Kobrinsky, M.J., Ramanathan, S., Park, C.M, Harmes, M., Ramachandrarao, Y., Park, H.M., Kloster, G., List, S., and Kim, S., Advanced Metallization Conference 2004 (AMC 2004), Oct. 19–21, 2004 (in press).Google Scholar
2. Guarini, K.W., Topol, A., Chan, V., Bernstein, K., Shi, L., Joshi, R., Haensch, W.E., and Ieong, M., Technology Venture Forum for 3D Architectures for Semiconductor Integration and Packaging (2004).Google Scholar
3. Pozder, S., Lu, J.-Q., Kwon, Y., Zollner, S., Yu, J., McMahon, J.J., Cale, T.S., Yu, K., and Gutmann, R.J., in Proceedings of the IEEE International Interconnect Technology Conference (IITC), 102–104 (2004).Google Scholar
4. http://www.tezzaron.com Google Scholar
5. Fan, A., Rahman, A., and Reif, R., Electrochemical and Solid-State Letters, 2 (10), 534–536 (1999).Google Scholar
6. Lu, J.-Q., Kwon, Y., McMahon, J. J., Jindal, A., Altemus, B., Cheng, D., Eisenbraun, E., Cale, T.S., and Gutmann, R.J., in Proceedings of 20th International VLSI Multilevel Interconnection Conference, Wade, T., Editor, 227–236 (2003).Google Scholar
7. http://www.sematech.org/corporate/news/releases/20040610a.htm Google Scholar
8. Schmidt, M.A., Proceedings of the IEEE, 86 (8), 1575–1585 (1998).Google Scholar
9. Murarka, S.P. and Fraser, D.B., J. Appl. Phys. 51 (1), 342–349 (1980).Google Scholar
10. Butz, R., Rubloff, G.W., and Ho, P.S., J. Vac. Sci. Technol. A 1 (2), 771–775 (1983).Google Scholar