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Aggressively Scaled P-Channel Mosfets With Stacked Nitride-Oxide-Nitride, N/O/N, Gate Dielectrics

Published online by Cambridge University Press:  10 February 2011

Yider Wu  and
Gerald Lucovsky
Yider Wu
Affiliation:
Departments of Electrical and Computer Engineering, and Physics, North Carolina State University, Raleigh, NC 27695-8202, USA
Gerald Lucovsky
Affiliation:
Departments of Electrical and Computer Engineering, and Physics, North Carolina State University, Raleigh, NC 27695-8202, USA
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Abstract

Ultrathin (tox,eq < 2.0 nm) Si3N4/SiO2(hereafter N/O) gate dielectrics with improved interface characteristics compared to devices with thermal oxides have been formed by remote plasma enhanced CVD of Si3N4onto oxides. If the Si-Si02 interface is intentionally nitrided prior to the Si3N4deposition, the increased physical thickness of the N/O stack combined with the interfacial nitridation reduces the direct tunneling current by more than two orders of magnitude. The ensuing device structure can then be characterized as N/O/N. The top nitride layer is also an effective boron diffusion barrier improving short channel characteristics in p+-poly PMOSFETs. In addition, nitrogen can also be transported to the silicon/dielectric interface during post-deposition RTAs, and this reduces degradation of transconductance during hot carrier stressing.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 567: Symposium R – Ultrathin SiO2 and Higg-K Materials for ULSI Gate Dielectrics , 1999 , 101
Copyright
Copyright © Materials Research Society 1999

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References

REFERENCES

[1] Hu, G. and Bruce, R., IEEE Trans. Elec. Dev. ED-32, 584 (1985).Google Scholar
[2] Wolf, S., Silicon procession for the VLSI Era, Vol. 3, Lattice Press, Sunset Beach, CA, p. 311, (1995).Google Scholar
[3] Pfiester, J. and Baker, F., IEEE Elec. Dev. Lett. 11, 247 (1990).10.1109/55.55269Google Scholar
[4] Mogami, T., Johansson, L., Sakai, I., and Fukuma, M., IEDM Tech. Dig. 533 (1991).Google Scholar
[5] Vogel, E., McLarty, P., and Wortman, J., IEEE Tran. Elec. Dev. ED- 43, 753 (1996).10.1109/16.491252Google Scholar
[6] Wu, Y. and Lucovsky, G., IEEE International Reliability Physics Symposium 70, (1998).Google Scholar
[7] Lo, S., Buchanan, D., Taur, Y., and Wang, W., IEEE Elec. Dev. Lett. 18, 209 (1997).10.1109/55.568766Google Scholar
[8] Alers, G., Werder, D., and Chabal, Y., Appl. Phys. Lett 73, 1517 (1998).10.1063/1.122191Google Scholar
[9] Hubbard, K. and Schlom, D., J. Mater. Res. 11, 2757 (1996).10.1557/JMR.1996.0350Google Scholar
[10] Parker, C., Lucovsky, G., and Hauser, J., IEEE Elec. Dev. Lett. 19, 106 (1998).10.1109/55.663529Google Scholar
[11] Ma, Y., Yasuda, T., and Lucovsky, G., Appl. Phys. Lett. 64, 2226 (1994).10.1063/1.111681Google Scholar
[12] Hattangady, S.V, Niimi, H. and Lucovsky, G., J. Vac. Sci. Technol. A 14, 3017 (1996).10.1116/1.580165Google Scholar
[13] Hattangady, S.V., Niimi, H., and Lucovsky, G., Appl. Phys. Lett. 66, 3495 (1995).10.1063/1.113775Google Scholar
[14] Wu, Y. and Lucovsky, G., IEEE Elec. Dev. Lett 19, 367 (1998).10.1109/55.720188Google Scholar
[15] Hauser, J., IEEE TED, 44, 1009 (1997)10.1109/16.585558Google Scholar
[16] Green, M. L. et al. , Appl. Phys. Lett. 65, 848, (1994).10.1063/1.112980Google Scholar
[17] Wristers, D., Han, L., and Kwong, D., Appl. Phys. Lett. 68, 2094 (1996).10.1063/1.115595Google Scholar
[18] Lucovsky, G. et al. Appl. Phys. Lett. 74 (April 5, 1999).10.1063/1.123728Google Scholar
[19] Yang, H., Niimi, H., Wu, Y. and Lucovsky, G., submitted to IEEE Elec. Dev. Lett. (1999).Google Scholar