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Amorphous Silicon 2-TFT Pixel Circuits on Stainless Steel Foils

Published online by Cambridge University Press:  01 February 2011

Alex Z Kattamis ,
I-Chun Cheng ,
Yongtaek Hong  and
Sigurd Wagner
Alex Z Kattamis
Affiliation:
kattamis@princeton.edu, Princeton University, Princeton Institute for the Science and Technology of Materials and the Department of Electrical Eng, E-Quad Building, Olden Street, Princeton, NJ, 08544, United States
I-Chun Cheng
Affiliation:
iccheng@princeton.edu, Princeton University, Princeton Institute for the Science and Technology of Materials & the Department of Electrical Eng, E-Quad Building, Olden Street, Princeton, NJ, 08544, United States
Yongtaek Hong
Affiliation:
yongtaek@snu.ac.kr, Eastman Kodak Company, Display Science & Technology Center, 1999 Lake Road, Rochester, NY, 14626, United States
Sigurd Wagner
Affiliation:
wagner@princeton.edu, Princeton University, Princeton Institute for the Science and Technology of Materials & the Department of Electrical Eng, E-Quad Building, Olden Street, Princeton, NJ, 08544, United States
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Abstract

We have fabricated pixel circuits consisting of two bottom-gate staggered source-drain amorphous silicon thin-film transistors (a-Si:H TFTs) on flexible stainless steel foils. Stainless steel is attractive because it allows for high processing temperatures of >300°C and is a perfect barrier to oxygen and moisture. Our steel foils were 75m thick, with a peak-to-peak surface roughness of >1.2m. This rough, as-rolled, conductive surface needed a thick planarization and passivation (electrical isolation) layer. The surface was planarized with 1.6m of spin-on-glass, which reduced the roughness to ~0.3m peak-to-peak. A passivation layer of 0.6m of SiNx deposited by plasma-enhanced chemical vapor deposition was used to reduce leakage currents and capacitive coupling to the substrate. The 92m × 369m voltage-programmed pixel circuits employ a switching (Sw) TFT (W/L=50/5m), a driver (Dr) TFT (W/L=200/5m), and a 2pF storage capacitor between the gate and source of the Dr TFT. With a supply voltage of VDD=20V and a drive bias of 20V the circuits deliver 26A of current. The vertical stripe pixels were integrated into 48 × (4) × 48 arrays and passivated with SiNx. Anode metal of Al-1% Si was also deposited, preparing the displays for subsequent OLED fabrication. Pixel circuits with this performance can drive top-emitting organic light emitting diodes (OLEDs) and therefore can be used in backplanes for flexible, high-resolution, active-matrix OLED displays.

Keywords

Siplasma-enhanced CVD (PECVD) (deposition)reactive ion etching
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 910: Symposium A – Amorphous and Polycrystalline Thin-Film Silicon Science and Technology – 2006 , 2006 , 0910-A16-03-L09-03
Copyright
Copyright © Materials Research Society 2006

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References

[1] Cannella, V., Izu, M., Jones, S., Wagner, S., and Cheng, I.-C., Information Display, pp.24–27, June, 2005.Google Scholar
[2] Long, K., Kattamis, A. Z., Cheng, I-C., Gleskova, H., Wagner, S. and Sturm, J. C., IEEE Elec Dev Lett., vol. 27, pp. 111–113, 2006.Google Scholar
[3] Wu, M., Bo, X., Sturm, J. C., and Wagner, S., IEEE Trans. Elec. Dev., vol. 49, pp. 1993–2000, 2002.Google Scholar
[4] Theiss, S. D., and Wagner, S., IEEE Elec. Dev. Lett., vol. 17, pp. 578–580, 1996.Google Scholar
[5] Hong, Y., Heiler, G., Cheng, I-C., Kattamis, A. Z., Wagner, S., IMID '05 Digest, vol. 28/3, pp. 892–896, 2005.Google Scholar
[6] Zaborowski, M., and Dumania, P., Microelec. Eng., vol. 50, pp. 301–309, 2000.Google Scholar