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An Asymmetric Dual Gate Poly-Si TFTs for Improving Hot Carrier Stress Stability and Kink Effect Suppression

Published online by Cambridge University Press:  01 February 2011

Joong Hyun Park
Affiliation:
jhpark@emlab.snu.ac.kr, Seoul National University, School of Electrical Engineering (#50), San 56-1, Sillim-dong, Gwanak-gu, Seoul, N/A, 151-742, Korea, Republic of
Woo Jin Nam
Affiliation:
jintree@emlab.snu.ac.kr, Seoul National University, School of Electrical Engineering (#50), San 56-1, Sillim-dong, Gwanak-gu, Seoul, N/A, 151-742, Korea, Republic of
Jae Hoon Lee
Affiliation:
jhlee@emlab.snu.ac.kr, Seoul National University, School of Electrical Engineering (#50), San 56-1, Sillim-dong, Gwanak-gu, Seoul, N/A, 151-742, Korea, Republic of
Min Koo Han
Affiliation:
mkh@snu.ac.kr, Seoul National University, School of Electrical Engineering (#50), San 56-1, Sillim-dong, Gwanak-gu, Seoul, N/A, 151-742, Korea, Republic of
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Abstract

An asymmetric dual gate poly-Si thin film transistors (TFTs), which is consist a long-gate TFT and a short-gate TFT, were fabricated in order to suppress the kink current and increase the reliability. The long-gate TFT operates in a linear regime and limits the total current flow by its current operation region. The asymmetric dual-gate does not exhibit from the kink current in a high drain bias due to the distribution of lateral electric field. The asymmetric dual-gate structure improves kink-free characteristics compared with conventional single and dual-gate TFTs. The hot-carrier stress reliability is successfully improved due to kink current suppression.

Type
Research Article
Copyright
Copyright © Materials Research Society 2006

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