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Channel engineering and junction overlap issues for ultra-shallow junctions formed by SPER in the 45 nm CMOS technology node

Published online by Cambridge University Press:  17 March 2011

Simone Severi ,
Kirklen Henson ,
Richard Lindsay ,
Anne Lauwers ,
Bartek J. Pawlak ,
Radu Surdeanu  and
K. De Meyer
Simone Severi
Affiliation:
IMEC, Kapeldreef 75, 3001 Leuven, Belgium K.U.Leuven, ESAT-INSYS, Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium
Kirklen Henson
Affiliation:
IMEC, Kapeldreef 75, 3001 Leuven, Belgium
Richard Lindsay
Affiliation:
IMEC, Kapeldreef 75, 3001 Leuven, Belgium
Anne Lauwers
Affiliation:
IMEC, Kapeldreef 75, 3001 Leuven, Belgium
Bartek J. Pawlak
Affiliation:
Philips Research Leuven
Radu Surdeanu
Affiliation:
Philips Research Leuven
K. De Meyer
Affiliation:
IMEC, Kapeldreef 75, 3001 Leuven, Belgium K.U.Leuven, ESAT-INSYS, Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium
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Abstract

The feasibility of the SPER junction process as a reasonable alternative to the spike anneal junction is proved in this work. Good control of the SCE and performance competitive results as compared to the spike junction are obtained. An analysis of the interaction between the halo dopant and the SPER junctions has been carried out; it is shown that the performance degrades with increasing halo dose as a consequence of an overlap resistance problem.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 810: Symposium C – Silicon Front-End Junction Formation-Physics and Technology , 2004 , C10.5
Copyright
Copyright © Materials Research Society 2004

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References

REFERENCES

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[5] Severi, S. et al. , ULIS'2003 ProceedingsGoogle Scholar