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Degradation Study of Ultra-thin JVD Silicon Nitride Mnsfets

Published online by Cambridge University Press:  01 February 2011

K. N. ManjulaRani ,
V. Ramgopal Rao  and
J. Vasi
K. N. ManjulaRani
Affiliation:
Department of Electrical Engineering Indian Institute of Technology, Bombay Mumbai 400076 India email: rani,rrao,vasi@ee.iitb.ac.in
V. Ramgopal Rao
Affiliation:
Department of Electrical Engineering Indian Institute of Technology, Bombay Mumbai 400076 India email: rani,rrao,vasi@ee.iitb.ac.in
J. Vasi
Affiliation:
Department of Electrical Engineering Indian Institute of Technology, Bombay Mumbai 400076 India email: rani,rrao,vasi@ee.iitb.ac.in
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Abstract

In this paper we discuss a new method for measuring border trap density (Nbt) in sub-micron transistors using the hysteresis in drain current. We have used this method to measure Nbt in jet Vapour Deposited (JVD) Silcon Nitride transistors (MNSFETs). We have extended this method to measure the energy and spatial distribution of border traps in these devices. The transient drain current varies linearly with logarthmic time. This suggests that tunneling is the dominant charge exchange mechanism of border traps. The pre-stress energy distribution is uniform whereas poststress energy distribution shows a peak near the midgap.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 716: Symposium B – Silicon Materials-Processing, Characterization, and Reliability , 2002 , B4.18
Copyright
Copyright © Materials Research Society 2002

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