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Published online by Cambridge University Press: 13 August 2013
Fabrication of integrated circuits is a multi-step process that involves chemical mechanical polishing (CMP) for planarizing the deposited layers. Although dependent on the consumables and machine operating conditions, most CMP researchers assume that the polishing occurs in the mixedlubrication regime, where the applied load on the wafer is supported by the hydrodynamic slurry pressure and the contact stress generated during the pad-wafer contact. The particle augmented mixed lubrication (PAML) approach has been employed by Terrell and Higgs (2009) as a high-fidelity asperity-scale mixed-lubrication CMP model. The current work introduces a more computationally efficient wafer-scale PAML model, called PAML-lite, which employs a two-dimensional average flow Reynold's Equation incorporating spatial dependence of entrainment velocities to model the hydrodynamic pressure. The contact mechanics are modeled using a Winkler elastic foundation in cylindrical polar coordinates. The resulting slurry hydrodynamic pressure distribution and contact stress are used to determine the equilibrium configuration of the system in the form of a nominal clearance and rolling and pitch angles. Local and wafer scale material removal rate (MRR) is predicted by assuming a uniform distribution of particle sizes. The prediction of PAML-lite were then benchmarked against experimental results. Upon verification, parametric studies were conducted to understand the effect of some unexplored CMP parameters.