Hostname: page-component-586b7cd67f-gb8f7 Total loading time: 0 Render date: 2024-11-24T12:39:51.359Z Has data issue: false hasContentIssue false
  • English
  • Français

Nickel Silicide Work Function Tuning Study In Metal-Gate CMOS Applications

Published online by Cambridge University Press:  26 February 2011

Jun Yuan ,
Grant Z. Pan ,
Yu-Lin Chao  and
Jason C.S. Woo
Jun Yuan
Affiliation:
Electrical Engineering Department, University of California, Los Angeles, CA, 90095
Grant Z. Pan
Affiliation:
Electrical Engineering Department, University of California, Los Angeles, CA, 90095
Yu-Lin Chao
Affiliation:
Electrical Engineering Department, University of California, Los Angeles, CA, 90095
Jason C.S. Woo
Affiliation:
Electrical Engineering Department, University of California, Los Angeles, CA, 90095
Get access

Abstract

Mid-gap work function (∼4.7eV) for mono-nickel-silicide (NiSi) was obtained by extrapolating flat band voltages of metal-oxide-semiconductor (MOS) capacitors with different gate oxide thickness. Both silicidation temperature and time can affect the nickel silicide work function as a result of different Ni:Si ratio close to the gate oxide interface. Arsenic implantation into the polysilicon before silicidation can shift the NiSi work function towards the silicon conduction band, which makes it suitable for high performance NMOS applications. The physical mechanism responsible for this work function shift is arsenic pile-up at the oxide interface during the nickel silicidation process. Therefore, dual work function metal gate can be obtained by using a single gate full silicidation process. Silicidation temperature and time also affect the work function shift from arsenic dopant, and the incomplete gate silicidation can have the maximum work function modification effect. Arsenic activation temperature before silicidation was found to have a significant effect on the work function shift. Un-annealed samples exhibit a minimum shift in work function due to the low dopant pile-up concentration at the oxide interface.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 829: Symposium B – Progress in Compound Semiconductor Materials IV – Electronic and Optoelectronic Applications , 2004 , B7.11
Copyright
Copyright © Materials Research Society 2005

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1: Yeo, Y.C., Lu, Q., et al, IEEE Elec. Dev. Lett, vol. 22, pp.227–229, May 2001 Google Scholar
2: Lavoie, C., d'Heurle, F.M., Detavernier, C., Cabral, C. Jr, Microelec. Eng. 70, pp. 144–157, 2003 Google Scholar
3: Xiang, Q., Goo, J.S., Pan, J., Yu, B., Ahmed, S., zhang, J., Lin, M.R., Symp.VLSI Tech. Dig. pp.103–1–4, 2003 Google Scholar
4: Kedzierski, J., Nowak, E., Kanarsky, T., et al., IEDM Tech. Dig., pp. 247–250, 2002 Google Scholar
5: Cheng, B., Maiti, B., Samayedam, S., Grant, J., et al, Proc. IEEE Int. SOI Conf., pp.91–92, 2001 Google Scholar
6: Polishchuk, I., Ranade, P., et al., IEEE Electron Dev. Lett., Vol.23, pp.200–202, Apr., 2002 Google Scholar
7: Lu, Q., Lin, R., Rande, P., et al., Symp. VLSI Tech. Dig., pp. 45–46, 2001 Google Scholar
8: Qin, M., Poon, Vincent M.C., and Ho, Stephen C.H., J. Electrochem. Soc., 148(5), p.G271, 2001 Google Scholar
9: Maszara, W., Krivokapic, Z., King, P. et al., IEDM Tech. Dig., p.367–370, 2002 Google Scholar
10: Kedzierski, J., Boyd, D., Ronsheim, P., et al., IEDM Tech. Dig., pp. 13.3.1–13.3.4, 2003 Google Scholar
11: Sim, J. H., Wen, H.C., Liu, J.P., et al., IEEE Electron Device Lett., Vol. 24, pp.631–633, Oct. 2003 Google Scholar
12: Maszara, W.P., J. Electrochem. Proc., pp. 341–353, 2004–2001 Google Scholar