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A Novel Low Temperature Self-Aligned Ti Silicide Technology for Sub-0.18 μm CMOS Devices

Published online by Cambridge University Press:  10 February 2011

L. P. Ren ,
P. Liu ,
G. Z. Pan  and
Jason C. S. Woo
L. P. Ren
Affiliation:
Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, CA90095-1594, ren@ee.ucla.edu
P. Liu
Affiliation:
Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, CA90095-1594, ren@ee.ucla.edu
G. Z. Pan
Affiliation:
Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, CA90095-1594, ren@ee.ucla.edu
Jason C. S. Woo
Affiliation:
Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, CA90095-1594, ren@ee.ucla.edu
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Abstract

A novel low temperature self-aligned Ti silicidation with Ge+ pre-amorphization implant (PAI) is presented. Compared to conventional high temperature PAI silicidation, the advantages of Ti salicidation at temperatures below the recrystallization of a pre-amorphized layer are: (1) C49 TiSi2 silicide formation occurs only in the pre-amorphized layer so that the silicide depth can be well controlled, forming a very sharp interface between the silicide and the Si substrate; (2) Ti just reacts with the amorphous layer, avoiding the so-called bridging issue in which the silicide grows laterally over the isolation or spacer; (3) the effects of metal thickness and substrate doping on silicide formation are suppressed.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 514: Symposium I – Advanced Interconnects & Contact Materials & Processes for… , 1998 , 245
Copyright
Copyright © Materials Research Society 1998

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References

REFERENCES

1. Kittl, J.A., Hong, Qi-Zhong, Rodder, Mark, Prinslow, Douglas A. and Misium, George R. Symposium on VLSI Technology Digest of Technical Papers, 1996, PP. 14–15.Google Scholar
2. Hsiao, T.C., Liu, P. and Woo, J.C., Digest IEEE SOI Conference, 1996, PP. 126–127.Google Scholar
3. Kittl, J.A., Hong, Qi-Zhong, Chao, Chih-Ping, Chen, Ih-Chin, Yu, Ning, O'Brien, Sean and Hanratty, Maureen, Symposium on VLSI Technology Digest of Technical Papers, 1997, PP. 103–104.Google Scholar
4. Hsiao, Tommy C., Liu, Ping, and Woo, Jason, IEEE TED, in press, 1998.Google Scholar
5. Apte, Pushkar P., Paranjpe, Ajit and Pollack, Gordon, IEEE Electron Device Letters, 17, 506 (1996).Google Scholar
6. Kittl, J.A., Prinslow, D.A., Misium, G. and Pas, M.F., Mat. Res. Soc. Symp. Proc. Vol.429, 175–180 (1996).Google Scholar