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Optimization of Ti and Co Self-Aligned Silicide RTP for 0.10 μm Cmos

Published online by Cambridge University Press:  10 February 2011

J. A. Kittl ,
Q. Z. Hong ,
H. Yang ,
N. Yu ,
M. Rodder ,
P. P. Apte ,
W. T. Shiau ,
C. P. Chao ,
T. Breedijk  and
M. F. Pas
J. A. Kittl
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, TX 75243, kittl@spdc.ti.com
Q. Z. Hong
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, TX 75243, kittl@spdc.ti.com
H. Yang
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, TX 75243, kittl@spdc.ti.com
N. Yu
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, TX 75243, kittl@spdc.ti.com
M. Rodder
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, TX 75243, kittl@spdc.ti.com
P. P. Apte
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, TX 75243, kittl@spdc.ti.com
W. T. Shiau
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, TX 75243, kittl@spdc.ti.com
C. P. Chao
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, TX 75243, kittl@spdc.ti.com
T. Breedijk
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, TX 75243, kittl@spdc.ti.com
M. F. Pas
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, TX 75243, kittl@spdc.ti.com
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Abstract

As CMOS technologies are scaled to 0.10 μm and beyond, self-aligned silicide (salicide) processes find difficult challenges. As junction depths and linewidths are scaled, achieving both low sheet resistance and low contact resistance maintaining low diode leakage becomes increasingly difficult. In this paper we present studies of Ti and Co salicide processes implemented into a 0.10 μm CMOS technology. We show that both for Ti and Co, the optimization of RTP parameters plays a crucial roll in achieving a successful implementation. For Co salicide, optimization of RTP conditions results in elimination of shallow junction leakage (its main scaling problem). Two-step RTP and one-step RTP Ti salicide processes are compared, showing the advantages of one-step RTP. The RTP process windows for low resistance narrow gates (the main scaling issue for Ti salicide) are analyzed. Processes with pre-amorphization, with Mo doping and with a combination of both are compared. An optimal process using Mo and preamorphization implants and one-step RTP is shown to result in excellent device characteristics and low resistance to 0.06 μm gates.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 525: Symposium W – Rapid Thermal & Integrated Processing VII , 1998 , 331
Copyright
Copyright © Materials Research Society 1998

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References

REFERENCES

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