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Recent Advances in 3D Integration at IMEC

Published online by Cambridge University Press:  26 February 2011

Piet De Moor ,
Wouter Ruythooren ,
Philippe Soussan ,
Bart Swinnen ,
Kris Baert ,
Chris Van Hoof  and
Eric Beyne
Piet De Moor
Affiliation:
demoor@imec.be, IMEC, MCP, Kapeldreef 75, Leuven, B-3001, Belgium
Wouter Ruythooren
Affiliation:
ruythooren@imec.be, IMEC, Kapeldreef 75, Leuven, B-3001, Belgium
Philippe Soussan
Affiliation:
soussan@imec.be, IMEC, Kapeldreef 75, Leuven, B-3001, Belgium
Bart Swinnen
Affiliation:
swinnen@imec.be, IMEC, Kapeldreef 75, Leuven, B-3001, Belgium
Kris Baert
Affiliation:
Kris.Baert@imec.be, IMEC, Kapeldreef 75, Leuven, B-3001, Belgium
Chris Van Hoof
Affiliation:
Chris.VanHoof@imec.be, IMEC, Kapeldreef 75, Leuven, B-3001, Belgium
Eric Beyne
Affiliation:
Eric.Beyne@imec.be, IMEC, Kapeldreef 75, Leuven, B-3001, Belgium
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Abstract

IMEC is focusing its 3D-integration technology developments in 3 distinct directions: 3D-System-in-a-Package (3D-SiP), 3D-Wafer-Level-Packaging (3D-WLP) and 3D-Stacked-IC (3D-SiC). First, the background of these separate approaches will be given. Next the materials and technologies involved, the typical characteristics and the ongoing developments will be discussed. Finally, the roadmap for the 3D-integration in IMEC will be presented.

Keywords

microelectronicsmicroelectro-mechanical (MEMS)thin film
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 970: Symposium Y – Enabling Technologies for 3-D Integration , 2006 , 0970-Y01-02
Copyright
Copyright © Materials Research Society 2007

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References

REFERENCES

1. Proc. of the 1st, 2nd and 3rd conf. on “3D Architectures for Semiconductor Integration and packaging”, RTI international, Burlingame, California, April 13–15, 2004; Tempe, Arizona, June 13–15, 2005; Burlingame, California, October 31 – November 2, 2006 Google Scholar
2. Beyne, E., “3D Interconnection and packaging: impending reality or still a dream?” proceedings of the IEEE International Solid-State Circuits Conference, ISSCC2004, 15–19 February 2004; San Francisco, CA, USA, IEEE, 2004, pp.138–145.Google Scholar
3. Beyne, E., “System-Driven Approaches to 3D Integration”, The 4th International Symposium on Microelectronics and Packaging, Seoul, S-Korea, September 28, 2005, p 25–34.Google Scholar
4. Noritake, C., Limaye, P., Gonzalez, M. and Vandevelde, B., “Thermal Cycle Reliability of 3D Chip Stacked Package Using Pb-free Solder Bumps: Parameter Study by FEM Analysis”, 7th Int. Conf. on Thermal, Mechanical and Multiphysics Simulation and Experiments in Microelectronics and Microsystems – EuroSimE, April 2006, Como (Italy).Google Scholar
5. Chen, Liu Caroline, Vandevelde, Bart, Swinnen, Bart, Beyne, Eric, “Enabling SPICE-Type Modeling of the Thermal Properties of 3D-Stacked Ics”, EPTC 2006, Singapore, December 6–8, 2006 Google Scholar
6. Gyselinckx, Bert, “3D System-in-Package Integration of Wireless Sensor Nodes”, invited paper at ISSCC, February 11–15 2007, San Francisco Google Scholar
7. De Munck, Koen, Bogaerts, Lieve, Tezcan, Deniz S., De Moor, Piet, Swinnen, Bart, Baert, Kris, and Van Hoof, Chris, “Wafer Level Temporary Bonding/Debonding for Thin Wafer Handling Applications”, IMAPS International Conference and Exhibition on Device Packaging, Scottsdale, March 2006 Google Scholar
8. Tezcan, Deniz Sabuncuoglu, Pham, Nga, Majeed, Bivragh, Baert, Kris, De Moor, Piet and Ruythooren, Wouter, “Sloped Through Wafer Vias for 3D Wafer Level Packaging”, accepted for publication at ECTC 2007, Reno, USA, May 29–June 1 2007.Google Scholar
9. Gonzalez, M. et al, “influence of dielectric materials and via geometry on the thermomechanical behaviour of silicon through interconnects” ”. Proc. of 10th Pan Pacific Microelectronics Symposium, SMTA, Hawaii, January 25–27, 2005.Google Scholar
10. Tezcan, Deniz Sabuncuoglu, De Munck, Koen, Pham, Nga, Luhn, Ole, Aarts, Arno, De Moor, Piet, Baert, Kris and Van Hoof, Chris, “Development of Vertical and Tapered Via Etch for 3D Through Wafer Interconnect Technology”, EPTC 2006, Singapore, December 6–8, 2006 Google Scholar
11. Pham, Nga P., Bulcke, Mathieu Vanden, De Moor, Piet, “Spray Coating of Photoresist for Realizing Through-Wafer Interconnects”, EPTC 2006, Singapore, December 6–8, 2006 Google Scholar
12. De Munck, Koen, Tezcan, Deniz Sabuncuoglu, Borgers, Tom, Ruythooren, Wouter, De Moor, Piet, Sedky, Sherif, Toccafondi, Cinzia, Bogaerts, Jan and Van Hoof, Chris, “High performance Hybrid and Monolithic Backside Thinned CMOS Imagers realized using a new integration process”, IEDM 2006, December 11–13 2006, San Francisco Google Scholar
13. Beyne, E., “Technologies for very high bandwidth electrical interconnects between next generation VLSI circuits”, IEEE-IEDM 2001 Technical Digest, December 2–5, Washington, D.C., S23–p3, 2001.Google Scholar
14. Vanden Bulcke, M. et al, “Active Electrode Arrays by Chip Embedding in a Flexible Silicone Carrier,” Engineering in Medicine and Biology Society, 2006. IEEE-EMBSGoogle Scholar
2006. 28th Annual International Conference of the, vol., no.pp. 2811–2815, 30 Aug.-03 Sept. 2006.Google Scholar
15. De Munck, K., Vaes, J., De Moor, P., Van Hoof, C., Swinnen, B., “Grinding and Mixed Silicon Cupper CMP of Stacked Patterned Wafers for 3D Integration”, MRS Fall Meeting, November 27 – December 1 2006, Boston Google Scholar
16. Ruythooren, Wouter, Stoukatch, Serguei, Lambrinou, Konstantina, De Moor, Piet, Swinnen, Bart, “Direct Cu-Cu Thermo-Compression Bonding for 3D-Stacked IC Integration”, IMAPS 2006, October 8–12, San Diego Google Scholar
17. Swinnen, B., Ruythooren, W., De Moor, P., Bogaerts, L., Carbonell, L., De Munck, K., Eyckens, B., Stoukatch, S., Tezcan, D. Sabuncuoglu, Tőkei, Z., Vaes, J., Van Aelst, J., Beyne, E., “3D integration by Cu Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias.”, IEDM 2006, December 11–13 2006, San Francisco Google Scholar