Hostname: page-component-78c5997874-8bhkd Total loading time: 0 Render date: 2024-11-19T12:43:14.522Z Has data issue: false hasContentIssue false
  • English
  • Français

Using a Barrier Layer to Inhibit Ti/Oxide Reaction to Reduce RC Delay and Improve Electromigration in Al-Cu/Ti/W Interconnect for High Power Analog and Mixed Signal Applications

Published online by Cambridge University Press:  01 February 2011

William Murphy ,
Tom C Lee ,
Jonathan Chapple-Sokol ,
Daniel A Delibac ,
Z. X. He ,
Stephen E Luce ,
Stephen A Mongeon ,
David C Thomas ,
Daniel S Vanslette  and
Timothy D Sullivan
William Murphy
Affiliation:
murphw@us.ibm.com, International Business Machines, AZQv, 1000 River Road, Bldg 975C, Essex Junction, VT, 05452, United States, 802-288-3477, 802-769-9452
Tom C Lee
Affiliation:
tomlee@us.ibm.com, International Business Machines, 1000 River Road, Essex Junction, VT, 05452, United States
Jonathan Chapple-Sokol
Affiliation:
chapple@us.ibm.com, International Business Machines, 1000 River Road, Essex Junction, VT, 05452, United States
Daniel A Delibac
Affiliation:
ddelibac@us.ibm.com, International Business Machines, 1000 River Road, Essex Junction, VT, 05452, United States
Z. X. He
Affiliation:
johnhe@us.ibm.com, International Business Machines, 1000 River Road, Essex Junction, VT, 05452, United States
Stephen E Luce
Affiliation:
sluce@us.ibm.com, International Business Machines, 1000 River Road, Essex Junction, VT, 05452, United States
Stephen A Mongeon
Affiliation:
smongeon@us.ibm.com, International Business Machines, 1000 River Road, Essex Junction, VT, 05452, United States
David C Thomas
Affiliation:
dcthomas@us.ibm.com, International Business Machines, 1000 River Road, Essex Junction, VT, 05452, United States
Daniel S Vanslette
Affiliation:
vansletd@us.ibm.com, International Business Machines, 1000 River Road, Essex Junction, VT, 05452, United States
Timothy D Sullivan
Affiliation:
tdsulliv@us.ibm.com, International Business Machines, 1000 River Road, Essex Junction, VT, 05452, United States
Get access

Abstract

In this paper, we report a novel method to improve aluminum interconnect electromigration performance, reduce metal line sheet resistance (Rs) and reduce via contact resistance (Rc) in a minimum pitch design. We report the effects of bottom redundancy layers on electrical line and via resistance and upstream electromigration performance. We studied 4 metallization stacks: (I) Ti/TiN/AlCu/Ti/TiN, (II) Ti/TiN/Ti/AlCu/Ti/TiN (annealed at 400°C for 20 minutes), (III) a flash process/stack I, (IV) stack III with aluminum deposition temperature of 250°C. Aluminum deposition temperature in stacks I, II, and III are 200°C. Bottom Ti/TiN, AlCu, and Top Ti/TiN layers have the same thickness for all these stacks. Metal line Rs and via contact resistances (Rc) of stack IV are 5% and 10% lower, respectively, than stack I. Stack II metal line sheet resistance is 15% higher than stack I, which is attributed to Al consumption in the TiAl3 formation during 400°C/20minutes annealing. Electromigration performance is best with stack IV followed by III, II, then I.

Keywords

electromigrationmetallic conductorbarrier layer
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1079: Symposium N – Materials and Processes for Advanced Interconnects for Microelectronics , 2008 , 1079-N09-01
Copyright
Copyright © Materials Research Society 2008

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. http://www.eetimes.com/showArticle.jhtml;jsessionid=QH2WVHB4JSY2SQSNDLRSKH0CJUNN2JVN?articleID=205602370 Google Scholar
2. Shohji, R., Uda, M., Nakamura, T., Yoda, T., Itoh, Y., IEEE Transactions, 1999, p. 302.Google Scholar
3. Matsumoto, S., Etoh, R., Ohtsuka, T., Ogawa, S., IITC, 1998, p. 113 Google Scholar
4. Grass, C., Le, H., McPherson, J., Haverman, R., IEEE/IRPS, 1994, p.173 Google Scholar
5. Skala, S., Bothra, S., IITC, 1998, p. 116.Google Scholar
6. Dion, M., IEEE IRW, 2000, p. 167.Google Scholar
7. Harmon, D., Gill, J., Sullivan, T., IRW, 1998, “Thermal Conductance of IC Interconnects Embedded in Dielectrics”Google Scholar