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Hot-Carrier Effect in Submicron pMOSFETs

Published online by Cambridge University Press:  15 February 2011

S. Saha ,
C. S. Yeh ,
Ph. Lindorfer ,
J. Luo ,
U. Nellore  and
B. Gadepally
S. Saha
Affiliation:
Fairchild Research Center, National Semiconductor Corporation, Santa Clara, CA 95052-8090
C. S. Yeh
Affiliation:
Fairchild Research Center, National Semiconductor Corporation, Santa Clara, CA 95052-8090
Ph. Lindorfer
Affiliation:
Fairchild Research Center, National Semiconductor Corporation, Santa Clara, CA 95052-8090
J. Luo
Affiliation:
Fairchild Research Center, National Semiconductor Corporation, Santa Clara, CA 95052-8090
U. Nellore
Affiliation:
Fairchild Research Center, National Semiconductor Corporation, Santa Clara, CA 95052-8090
B. Gadepally
Affiliation:
Fairchild Research Center, National Semiconductor Corporation, Santa Clara, CA 95052-8090
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Abstract

This paper describes an application of process and device simulation programs in the study of substrate current generated by hot-carrier effect in submicron p-channel MOSFET devices. The impact ionization model for holes was calibrated for accurate simulation of substrate current in submicron devices, and an expression for the impact ionization rate of holes in silicon is obtained. The simulated substrate current for 0.57, 0.73 and 1.13 μm devices obtained by the optimized expression agrees very well with the measured data. The optimized impact ionization expression was also used to simulate the effect of p- Lightly Doped Drain impurity profile on substrate current, and the simulated peak substrate current and the corresponding maximum lateral channel electric field as a function of p- dose and length are presented.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 391: Symposium T – Materials Reliability in Microelectronics V , 1995 , 21
Copyright
Copyright © Materials Research Society 1995

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