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Modeling and Simulation of Parasitic Effects in Stacked Silicon

Published online by Cambridge University Press:  26 February 2011

Gunter Elst
Gunter Elst*
Affiliation:
elst@eas.iis.fraunhofer.de, Fraunhofer IIS, Design Automation, Zeunerstrasse 38, Dresden, 01069, Germany
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Abstract

Devices and interconnect structures of new semiconductor and packaging technologies show parasitic physical effects with a growing influences of the system behavior. Therefore, the design technology has to be developed and adjusted to ensure high system performance and reliability of these very complex systems on chip and in a stack. The influences of parasitic effects on the circuit behavior have to be minimized within the design process.

Typical parasitic effects of the Vertical System Integration (VSI®) by stacked silicon are discussed in this paper. Effects like electro thermal coupling, electromagnetic interactions, and the sensitivity due to parameter variations and their influence to the system behavior are identified and modeled. Approaches for minimization of these influences by design modifications are presented.

Keywords

microelectronicssimulationthermoelectricity
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 970: Symposium Y – Enabling Technologies for 3-D Integration , 2006 , 0970-Y02-02
Copyright
Copyright © Materials Research Society 2007

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References

REFERENCES

[1] De Man, H., “Ambient Intelligence: Broad Dreams and Nanoscale Realities”, IEEE International Solid-State Circuit Conference ISSCC 2005, San Francisco, February 6–10 Google Scholar
[2] Klumpp, A., Merkel, R., Weber, J., Wieland, R., Elst, G., Ramm, P,.“Vertical System Integration Technology for High Speed Applications by Using Inter-Chip Vias and Solid-Liquid Interdiffusion Bonding”, in “The World of Electronic Packaging and System Integration”, ddp goldenbogen, Dresden 2004, pp 42–47 Google Scholar
[3] Benkart, P., Heittmann, A., Huebner, H., Ramacher, U., “3D Chip Stack Technology using Through-Chip Interconnects”, IEEE Design & Test of Computers, 2005, pp 512–518 Google Scholar
[4] Ababei, C., Feng, Y., Golpen, B., Mogal, H., Zhang, T., Bazargan, K., Sapatnekar, S., “Placement and Routing in 3D Integrated Circuits”, IEEE Design & Test of Computers, 2005, pp 520–530 Google Scholar
[5] Kyu Lim, S., “Physical Design for 3D System in Package”, IEEE Design & Test of Computers, 2005, pp 532–538 Google Scholar
[6] Schneider, P. and others, “Modeling and Simulation”, deliverable report 2006-07-27, integrated project e-CUBES, IST-026461, February 2006–January 2009 Google Scholar