Hostname: page-component-586b7cd67f-g8jcs Total loading time: 0 Render date: 2024-11-27T14:28:04.111Z Has data issue: false hasContentIssue false

Sequential Process Modeling for Determining Process-Induced Thermal Stress in Advanced Cu/Low-k Interconnects

Published online by Cambridge University Press:  01 February 2011

Kwanho Yang
Affiliation:
The Dow Chemical Company, Advanced Electronic Materials, Midland, MI, 48674
Joost J. Waeterloos
Affiliation:
The Dow Chemical Company, Advanced Electronic Materials, Midland, MI, 48674
Jang-Hi Im
Affiliation:
The Dow Chemical Company, Advanced Electronic Materials, Midland, MI, 48674
Michael E. Mills
Affiliation:
The Dow Chemical Company, Advanced Electronic Materials, Midland, MI, 48674
Get access

Abstract

The thermomechanical reliability of Cu/low-k interconnects, which is directly related to yield problems and premature device failures, has been a major issue. The development of a manufacturing process, which can satisfy the most stringent reliability standards, requires detailed information on the thermomechanical behavior of Cu/low-k interconnects. The thermomechanical behavior of Cu/low-k interconnects is complicated by the fact that processinduced thermal stresses are developed during the manufacturing process. A conventional finite element analysis (FEA) approach has some difficulties to model Cu/low-k interconnects that keep changing during process steps. Therefore, a sequential process modeling technique has been developed to simulate the interconnect behavior to substantially any level of detail and understand the complex thermomechanical behavior of Cu/low-k interconnects while being manufactured. In this paper, we briefly describe a sequential process modeling technique and demonstrate how we use the modeling technique to solve a Cu/SiC delamination problem in a Cu/SiLK* semiconductor dielectric dual damascene test structure.

Type
Research Article
Copyright
Copyright © Materials Research Society 2003

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

[1] http://ublic.itrs.net/Google Scholar
[2] Gan, D., Wang, G., Ho, P.S., Morrow, X. and Leu, J., Proc. Int. Interconnect Tech. Conf. 2002, pp. 271273.Google Scholar
[3] Mercado, L., Goldberg, C., Kuo, S., Proc. Int. Interconnect Tech. Conf. 2002, pp. 119121.Google Scholar
[4] Gonda, V., Toonder, J.M.J. Den, Beijer, J., Zhang, G.Q., Hoofman, R.J.O.M., Ernst, L.J., Proc. Of EuroSIME 2003, pp. 359363.Google Scholar